[Bug 1295738] Re: [4.8 Regression] unable to find a register to spill in class 'LO_REGS'

[Kumar Venkataramanan]

There is difference in machine descritptions writtem for *ior_scc_scc pattern.
 
GCC 4.8 branch, *ior_scc_scc pattern is 

(define_insn_and_split "*ior_scc_scc"
  [(set (match_operand:SI 0 "s_register_operand" "=r")
        (ior:SI (match_operator:SI 3 "arm_comparison_operator"
                 [(match_operand:SI 1 "s_register_operand" "r")
                  (match_operand:SI 2 "arm_add_operand" "rIL")])
                (match_operator:SI 6 "arm_comparison_operator"
                 [(match_operand:SI 4 "s_register_operand" "r")
                  (match_operand:SI 5 "arm_add_operand" "rIL")])))
   (clobber (reg:CC CC_REGNUM))]

In GCC 4.9 tunk

(define_insn_and_split "*ior_scc_scc"
  [(set (match_operand:SI 0 "s_register_operand" "=Ts")
        (ior:SI (match_operator:SI 3 "arm_comparison_operator"
                 [(match_operand:SI 1 "s_register_operand" "r")
                  (match_operand:SI 2 "arm_add_operand" "rIL")])
                (match_operator:SI 6 "arm_comparison_operator"
                 [(match_operand:SI 4 "s_register_operand" "r")
                  (match_operand:SI 5 "arm_add_operand" "rIL")])))
   (clobber (reg:CC CC_REGNUM))]

Which defines a new constarint "Ts"and gives it general register set
when "it" support is not restriccted

(define_register_constraint "Ts" "(arm_restrict_it) ? LO_REGS : GENERAL_REGS"
 "For arm_restrict_it the core registers @code{r0}- at code{r7}.  GENERAL_REGS otherwise."

This is the only difference in machinde descriptions. But this does not
fixes the bug.  I still count on LRA is able to satisfy the constraint
while reload still fails even in trunk.

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https://bugs.launchpad.net/bugs/1295738

Title:
  [4.8 Regression] unable to find a register to spill in class 'LO_REGS'

Status in The GNU Compiler Collection:
  New
Status in Linaro GCC:
  New
Status in “gcc-4.8” package in Ubuntu:
  New

Bug description:
  seen with the 4.8 branch on arm-linux-gnueabihf, configured with
  --with-arch=armv7-a --with-fpu=vfpv3-d16 --with-float=hard --with-mode=thumb 

  omitting the -fno-tree-dce works around the issue.  not seen with the
  4.7 branch and trunk 20140306.

  $ g++ -std=c++11 -fPIC -fno-tree-dce -fno-exceptions -fno-omit-frame-pointer -c -g -O2 JITArithmetic32_64.ii
  ../Source/JavaScriptCore/jit/JITArithmetic32_64.cpp: In member function 'void JSC::JIT::emit_op_add(JSC::Instruction*)':
  ../Source/JavaScriptCore/jit/JITArithmetic32_64.cpp:526:1: error: unable to find a register to spill in class 'LO_REGS'
  ../Source/JavaScriptCore/jit/JITArithmetic32_64.cpp:526:1: error: this is the insn:
  (insn 335 334 336 20 (parallel [
              (set (reg:SI 3 r3)
                  (ior:SI (eq:SI (reg/v:SI 112 [ op ])
                          (reg/v:SI 110 [ dst ]))
                      (eq:SI (reg/v:SI 111 [ op ])
                          (reg/v:SI 110 [ dst ]))))
              (clobber (reg:CC 100 cc))
          ]) ../Source/JavaScriptCore/jit/JITArithmetic32_64.cpp:514 295 {*ior_scc_scc}
       (expr_list:REG_UNUSED (reg:CC 100 cc)
          (nil)))
  ../Source/JavaScriptCore/jit/JITArithmetic32_64.cpp:526: confused by earlier errors, bailing out
  Preprocessed source stored into /tmp/ccb0Osgc.out file, please attach this to your bugreport.

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