[Bug 1995848] Re: [SRU] provide package u-boot-microchip

[Launchpad Bug Tracker]

This bug was fixed in the package u-boot - 2022.01+dfsg-2ubuntu2.1

---------------
u-boot (2022.01+dfsg-2ubuntu2.1) jammy; urgency=medium

  * Add package u-boot-microchip (LP: #1995848)
  * Add u-boot-sifive.README.Debian
  * Enable reset via SBI
    d/p/riscv64/sysreset-sbi.patch
    d/p/enable-reset-via-SBI-on-PolarFire-Icicle-Kit.patch

 -- Heinrich Schuchardt <heinrich.schuchardt at canonical.com>  Fri, 18 Nov
2022 12:11:50 +0100

** Changed in: u-boot (Ubuntu Jammy)
       Status: Fix Committed => Fix Released

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Title:
  [SRU] provide package u-boot-microchip

Status in u-boot package in Ubuntu:
  Fix Released
Status in u-boot source package in Jammy:
  Fix Released

Bug description:
  [ Impact ]

  The PolarFire Icicle Kit development board provides good upstream
  support. Microchip plans to ship this boards for a long time. We
  should enable the hardware in the Jammy LTS release. This requires
  providing U-Boot.

  The rebuild will be based on OpenSBI 1.1 which will we copied to Jammy
  with #1995261.

  We will enable reset via SBI for all RISC-V platforms with patch
  d/p/riscv64/sysreset-sbi.patch.

  For Jammy the package u-boot-microchip is new. Booting in Jammy will
  depend on a 5.19 kernel.

  [ Test Plan ]

  Due to the updated OpenSBI we will have to retest all Ubuntu Jammy
  supported RISC-V U-Boot platforms (Unmatched, QEMU) plus the PolarFire
  Icicle kit (VisionFive comes with its own U-Boot on SPI flash,
  Allwinner Nezha D1 uses separate package u-boot-nezha):

  * Boot preinstalled images.
  * Update U-Boot.
  * Install clang and run 'clang -v' (This failed on the Nezha platform with an older OpenSBI).
  * Test reset from Linux.
  * Test poweroff from Linux (SiFive HiFive Unmatched and QEMU).

  [ Where problems could occur ]

  Booting, resetting, and poweroff of all RISC-V platforms might fail
  due to the updated OpenSBI.

  The updated OpenSBI might lead to failures due to incorrect emulation
  of unimplemented RISC-V instructions or incorrect interrupt handling.

  [ Other Info ]

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