[Bug 2108997] Comment bridged from LTC Bugzilla
bugproxy
2108997 at bugs.launchpad.net
Thu Jan 29 16:40:01 UTC 2026
------- Comment From JREMUS at de.ibm.com 2026-01-29 11:31 EDT-------
Verification of Binutils shows a few missing instructions, missing instruction format changes, and mnemonic parsing differences:
root at b3545006:~# apt install -t noble-proposed binutils
root at b3545006:~# apt-cache policy binutils
binutils:
Installed: 2.42-4ubuntu2.9
Candidate: 2.42-4ubuntu2.9
Version table:
*** 2.42-4ubuntu2.9 100
100 http://ports.ubuntu.com/ubuntu-ports noble-proposed/main s390x Packages
100 /var/lib/dpkg/status
2.42-4ubuntu2.8 500
500 http://ports.ubuntu.com/ubuntu-ports noble-updates/main s390x Packages
500 http://ports.ubuntu.com/ubuntu-ports noble-security/main s390x Packages
2.42-4ubuntu2 500
500 http://ports.ubuntu.com/ubuntu-ports noble/main s390x Packages
root at b3545006:~# apt-src install binutils
root at b3545006:~# git clone -b binutils-2_45
git://sourceware.org/git/binutils-gdb.git
# diff -u ~/binutils-2.42/opcodes/s390-opc.txt ~/binutils-gdb/opcodes/s390-opc.txt
[Using Beyond Compare to ignore unimportant differences]
--- ~/binutils-2.42/opcodes/s390-opc.txt
+++ ~/binutils-gdb/opcodes/s390-opc.txt
@@ -2184,0 +2193,8 @@
+c806 cal SSF_RRDRD2 "compare and load 32" arch15 zarch
+c807 calg SSF_RRDRD2 "compare and load 64" arch15 zarch
+c80f calgf SSF_RRDRD2 "compare and load 64<32" arch15 zarch
+eb0000000016 pfcr RSY_RRRD "perform functions with concurrent results" arch15 zarch
# diff -u ~/binutils-2.42/opcodes/s390-opc.c ~/binutils-gdb/opcodes/s390-opc.c
[Using Beyond Compare to ignore unimportant differences]
--- ~/binutils-2.42/opcodes/s390-opc.c
+++ ~/binutils-gdb/opcodes/s390-opc.c
@@ -216,15 +218,9 @@
{ 4, 36, 0 },
#define U8_8 (U4_36 + 1) /* 8 bit unsigned value starting at 8 */
{ 8, 8, 0 },
-#define U6_18 (U8_8 + 1) /* 6 bit unsigned value starting at 18 */
- { 6, 18, 0 },
-#define U8_16 (U6_18 + 1) /* 8 bit unsigned value starting at 16 */
+#define U8_16 (U8_8 + 1) /* 8 bit unsigned value starting at 16 */
{ 8, 16, 0 },
-#define U5_27 (U8_16 + 1) /* 5 bit unsigned value starting at 27 */
- { 5, 27, 0 },
-#define U6_26 (U5_27 + 1) /* 6 bit unsigned value starting at 26 */
- { 6, 26, 0 },
-#define U8_24 (U6_26 + 1) /* 8 bit unsigned value starting at 24 */
+#define U8_24 (U8_16 + 1) /* 8 bit unsigned value starting at 24 */
{ 8, 24, 0 },
#define U8_28 (U8_24 + 1) /* 8 bit unsigned value starting at 28 */
{ 8, 28, 0 },
@@ -326,9 +322,9 @@
#define INSTR_RIE_R0U0 6, { R_8,U16_16,0,0,0,0 } /* e.g. clfitne */
#define INSTR_RIE_RUI0 6, { R_8,I16_16,U4_12,0,0,0 } /* e.g. lochi */
#define INSTR_RIE_RRUUU 6, { R_8,R_12,U8_16,U8_24,U8_32,0 } /* e.g. rnsbg */
-#define INSTR_RIE_RRUUU2 6, { R_8,R_12,U8_16,U6_26,U8_32,0 } /* e.g. risbgz */
-#define INSTR_RIE_RRUUU3 6, { R_8,R_12,U8_16,U5_27,U8_32,0 } /* e.g. risbhg */
-#define INSTR_RIE_RRUUU4 6, { R_8,R_12,U6_18,U8_24,U8_32,0 } /* e.g. rnsbgt */
+#define INSTR_RIE_RRUUU2 INSTR_RIE_RRUUU /* e.g. risbgz */
+#define INSTR_RIE_RRUUU3 INSTR_RIE_RRUUU /* e.g. risbhg */
+#define INSTR_RIE_RRUUU4 INSTR_RIE_RRUUU /* e.g. rnsbgt */
#define INSTR_RIL_0P 6, { J32_16,0,0,0,0 } /* e.g. jg */
#define INSTR_RIL_RP 6, { R_8,J32_16,0,0,0,0 } /* e.g. brasl */
#define INSTR_RIL_UP 6, { U4_8,J32_16,0,0,0,0 } /* e.g. brcl */
@@ -472,6 +468,7 @@
#define INSTR_SS_RRRDRD2 6, { R_8,D_20,B_16,R_12,D_36,B_32 } /* e.g. plo */
#define INSTR_SS_RRRDRD3 6, { R_8,R_12,D_20,B_16,D_36,B_32 } /* e.g. lmd */
#define INSTR_SSF_RRDRD 6, { D_20,B_16,D_36,B_32,R_8,0 } /* e.g. mvcos */
+#define INSTR_SSF_RRDRD2 6, { R_8,D_20,B_16,D_36,B_32,0 } /* e.g. cal */
#define INSTR_SSF_RERDRD2 6, { RE_8,D_20,B_16,D_36,B_32,0 } /* e.g. lpd */
#define INSTR_S_00 4, { 0,0,0,0,0,0 } /* e.g. hsch */
#define INSTR_S_RD 4, { D_20,B_16,0,0,0,0 } /* e.g. stck */
@@ -558,9 +555,9 @@
#define MASK_RIE_R0U0 { 0xff, 0x0f, 0x00, 0x00, 0xff, 0xff }
#define MASK_RIE_RUI0 { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff }
#define MASK_RIE_RRUUU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
-#define MASK_RIE_RRUUU2 { 0xff, 0x00, 0x00, 0xc0, 0x00, 0xff }
-#define MASK_RIE_RRUUU3 { 0xff, 0x00, 0x00, 0xe0, 0x00, 0xff }
-#define MASK_RIE_RRUUU4 { 0xff, 0x00, 0xc0, 0x00, 0x00, 0xff }
+#define MASK_RIE_RRUUU2 { 0xff, 0x00, 0x00, 0x80, 0x00, 0xff }
+#define MASK_RIE_RRUUU3 { 0xff, 0x00, 0x00, 0x80, 0x00, 0xff }
+#define MASK_RIE_RRUUU4 { 0xff, 0x00, 0x80, 0x00, 0x00, 0xff }
#define MASK_RIL_0P { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
#define MASK_RIL_RP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
#define MASK_RIL_UP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
@@ -704,6 +701,7 @@
#define MASK_SS_RRRDRD2 { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
#define MASK_SS_RRRDRD3 { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
#define MASK_SSF_RRDRD { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
+#define MASK_SSF_RRDRD2 { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
#define MASK_SSF_RERDRD2 { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
#define MASK_S_00 { 0xff, 0xff, 0xff, 0xff, 0x00, 0x00 }
#define MASK_S_RD { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
# diff -ur ~/binutils-2.42/gas/testsuite/gas/s390 ~/binutils-gdb/gas/testsuite/gas/s390
[Reduced to hopfeully all relevant ones]
diff -ur ~/binutils-2.42/gas/testsuite/gas/s390/zarch-arch15.d ~/binutils-gdb/gas/testsuite/gas/s390/zarch-arch15.d
--- ~/binutils-2.42/gas/testsuite/gas/s390/zarch-arch15.d
+++ ~/binutils-gdb/gas/testsuite/gas/s390/zarch-arch15.d
@@ -100,3 +100,7 @@
.*: e6 0f 00 00 00 5f [ ]*vtp %v15
.*: e6 0f 0f ff d0 5f [ ]*vtp %v15,65533
.*: e6 0f 1f ff d2 7f [ ]*vtz %v15,%v17,65533
+.*: c8 36 10 0a 20 14 [ ]*cal %r3,10\(%r1\),20\(%r2\)
+.*: c8 37 10 0a 20 14 [ ]*calg %r3,10\(%r1\),20\(%r2\)
+.*: c8 3f 10 0a 20 14 [ ]*calgf %r3,10\(%r1\),20\(%r2\)
+.*: eb 13 28 f0 fd 16 [ ]*pfcr %r1,%r3,-10000\(%r2\)
diff -ur ~/binutils-2.42/gas/testsuite/gas/s390/zarch-arch15.s ~/binutils-gdb/gas/testsuite/gas/s390/zarch-arch15.s
--- ~/binutils-2.42/gas/testsuite/gas/s390/zarch-arch15.s
+++ ~/binutils-gdb/gas/testsuite/gas/s390/zarch-arch15.s
@@ -94,3 +94,7 @@
vtp %v15
vtp %v15,65533
vtz %v15,%v17,65533
+ cal %r3,10(%r1),20(%r2)
+ calg %r3,10(%r1),20(%r2)
+ calgf %r3,10(%r1),20(%r2)
+ pfcr %r1,%r3,-10000(%r2)
diff -ur ~/binutils-2.42/gas/testsuite/gas/s390/zarch-optargs.d ~/binutils-gdb/gas/testsuite/gas/s390/zarch-optargs.d
--- ~/binutils-2.42/gas/testsuite/gas/s390/zarch-optargs.d
+++ ~/binutils-gdb/gas/testsuite/gas/s390/zarch-optargs.d
@@ -6,7 +6,45 @@
Disassembly of section .text:
.* <foo>:
-.*: e7 00 00 10 00 0e [ ]*vst %v0,16
-.*: e7 00 00 10 30 0e [ ]*vst %v0,16,3
-.*: e7 00 20 10 00 0e [ ]*vst %v0,16\(%r2\)
-.*: e7 00 20 10 30 0e [ ]*vst %v0,16\(%r2\),3
+# nopr [R1]
+.*: 07 00 [ ]*nopr
+.*: 07 01 [ ]*nopr %r1
+# nop [D1(X1,B1)]
+.*: 47 00 00 00 [ ]*nop
+.*: 47 00 0f ff [ ]*nop 4095
+.*: 47 00 2f ff [ ]*nop 4095\(%r2\)
+.*: 47 01 0f ff [ ]*nop 4095\(%r1,0\)
+.*: 47 01 2f ff [ ]*nop 4095\(%r1,%r2\)
+# cu12 R1,R2[,M3]
+.*: b2 a7 00 24 [ ]*cutfu %r2,%r4
+.*: b2 a7 30 24 [ ]*cu12 %r2,%r4,3
+# vst V1,D2(X2,B2)[,M3]
+.*: e7 10 00 10 00 0e [ ]*vst %v1,16
+.*: e7 10 00 10 30 0e [ ]*vst %v1,16,3
+.*: e7 10 30 10 00 0e [ ]*vst %v1,16\(%r3\)
+.*: e7 10 30 10 30 0e [ ]*vst %v1,16\(%r3\),3
+.*: e7 12 00 10 00 0e [ ]*vst %v1,16\(%r2,0\)
+.*: e7 12 00 10 30 0e [ ]*vst %v1,16\(%r2,0\),3
+.*: e7 12 30 10 00 0e [ ]*vst %v1,16\(%r2,%r3\)
+.*: e7 12 30 10 30 0e [ ]*vst %v1,16\(%r2,%r3\),3
+# idte R1,R3,R2[,M4]
+.* b9 8e 30 12 [ ]*idte %r1,%r3,%r2
+.* b9 8e 34 12 [ ]*idte %r1,%r3,%r2,4
+# ipte R1,R2[,R3[,M4]]
+.* b2 21 00 12 [ ]*ipte %r1,%r2
+.* b2 21 30 12 [ ]*ipte %r1,%r2,%r3
+.* b2 21 34 12 [ ]*ipte %r1,%r2,%r3,4
+# vstm V1,V3,D2(B2)[,M4]
+.*: e7 13 00 10 00 3e [ ]*vstm %v1,%v3,16
+.*: e7 13 00 10 40 3e [ ]*vstm %v1,%v3,16,4
+.*: e7 13 20 10 00 3e [ ]*vstm %v1,%v3,16\(%r2\)
+.*: e7 13 20 10 40 3e [ ]*vstm %v1,%v3,16\(%r2\),4
+# risbg R1,R2,I3,I4[,I5]
+.*: ec 12 03 04 00 55 [ ]*risbg %r1,%r2,3,4
+.*: ec 12 03 04 05 55 [ ]*risbg %r1,%r2,3,4,5
+# vfae V1,V2,V3,M4[,M5]
+.*: e7 12 30 00 40 82 [ ]*vfae %v1,%v2,%v3,4
+.*: e7 12 30 50 40 82 [ ]*vfae %v1,%v2,%v3,4,5
+# vstrc V1,V2,V3,V4,M5[,M6]
+.*: e7 12 35 00 40 8a [ ]*vstrc %v1,%v2,%v3,%v4,5
+.*: e7 12 35 60 40 8a [ ]*vstrc %v1,%v2,%v3,%v4,5,6
diff -ur ~/binutils-2.42/gas/testsuite/gas/s390/zarch-optargs.s ~/binutils-gdb/gas/testsuite/gas/s390/zarch-optargs.s
--- ~/binutils-2.42/gas/testsuite/gas/s390/zarch-optargs.s
+++ ~/binutils-gdb/gas/testsuite/gas/s390/zarch-optargs.s
@@ -1,6 +1,44 @@
.text
foo:
- vst %v0,16
- vst %v0,16,3
- vst %v0,16(%r2)
- vst %v0,16(%r2),3
+# nopr [R1]
+ nopr
+ nopr %r1
+# nop [D1(X1,B1)]
+ nop
+ nop 4095
+ nop 4095(%r2)
+ nop 4095(%r1,0)
+ nop 4095(%r1,%r2)
+# cu12 R1,R2[,M3]
+ cu12 %r2,%r4
+ cu12 %r2,%r4,3
+# vst V1,D2(X2,B2)[,M3]
+ vst %v1,16
+ vst %v1,16,3
+ vst %v1,16(%r3)
+ vst %v1,16(%r3),3
+ vst %v1,16(%r2,0)
+ vst %v1,16(%r2,0),3
+ vst %v1,16(%r2,%r3)
+ vst %v1,16(%r2,%r3),3
+# idte R1,R3,R2[,M4]
+ idte %r1,%r3,%r2
+ idte %r1,%r3,%r2,4
+# ipte R1,R2[,R3[,M4]]
+ ipte %r1,%r2
+ ipte %r1,%r2,%r3
+ ipte %r1,%r2,%r3,4
+# vstm V1,V3,D2(B2)[,M4]
+ vstm %v1,%v3,16
+ vstm %v1,%v3,16,4
+ vstm %v1,%v3,16(%r2)
+ vstm %v1,%v3,16(%r2),4
+# risbg R1,R2,I3,I4[,I5]
+ risbg %r1,%r2,3,4
+ risbg %r1,%r2,3,4,5
+# vfae V1,V2,V3,M4[,M5]
+ vfae %v1,%v2,%v3,4
+ vfae %v1,%v2,%v3,4,5
+# vstrc V1,V2,V3,V4,M5[,M6]
+ vstrc %v1,%v2,%v3,%v4,5
+ vstrc %v1,%v2,%v3,%v4,5,6
# diff -u ~/binutils-2.42/gas/config/tc-s390.c ~/binutils-gdb/gas/config/tc-s390.c
[Using Beyond Compare to ignore unimportant differences]
--- ~/binutils-2.42/gas/config/tc-s390.c
+++ ~/binutils-gdb/gas/config/tc-s390.c
@@ -1221,17 +1374,39 @@
+static unsigned int
+operand_count (const unsigned char *opindex_ptr)
+{
+ unsigned int count = 0;
+ for (; *opindex_ptr != 0; opindex_ptr++)
+ {
+ if (!(s390_operands[*opindex_ptr].flags & (S390_OPERAND_DISP
+ | S390_OPERAND_INDEX
+ | S390_OPERAND_LENGTH)))
+ count++;
+ }
+ return count;
+}
/* Return true if all remaining operands in the opcode with
OPCODE_FLAGS can be skipped. */
static bool
skip_optargs_p (unsigned int opcode_flags, const unsigned char *opindex_ptr)
{
- if ((opcode_flags & (S390_INSTR_FLAG_OPTPARM | S390_INSTR_FLAG_OPTPARM2))
- && opindex_ptr[0] != '\0'
- && opindex_ptr[1] == '\0')
+ if ((opcode_flags & (S390_INSTR_FLAG_OPTPARM | S390_INSTR_FLAG_OPTPARM2)))
+ {
+ unsigned int opcount = operand_count (opindex_ptr);
+ if (opcount == 1)
return true;
- if ((opcode_flags & S390_INSTR_FLAG_OPTPARM2)
- && opindex_ptr[0] != '\0'
- && opindex_ptr[1] != '\0'
- && opindex_ptr[2] == '\0')
+ if ((opcode_flags & S390_INSTR_FLAG_OPTPARM2) && opcount == 2)
return true;
+ }
return false;
}
@@ -1263,6 +1437,7 @@
expressionS ex;
elf_suffix_type suffix;
bfd_reloc_code_real_type reloc;
- int skip_optional;
+ int omitted_index;
char *f;
int fc, i;
@@ -1270,8 +1445,8 @@
while (ISSPACE (*str))
str++;
- skip_optional = 0;
/* Gather the operands. */
+ omitted_index = 0; /* Whether X in D(X,B) was omitted. */
fc = 0;
for (opindex_ptr = opcode->operands; *opindex_ptr != 0; opindex_ptr++)
@@ -1280,8 +1455,7 @@
operand = s390_operands + *opindex_ptr;
- if ((opcode->flags & (S390_INSTR_FLAG_OPTPARM | S390_INSTR_FLAG_OPTPARM2))
- && *str == '\0')
+ if (*str == '\0' && skip_optargs_p (opcode->flags, opindex_ptr))
{
/* Optional parameters might need to be ORed with a
value so calling s390_insert_operand is needed. */
@@ -1289,13 +1463,17 @@
break;
}
- if (skip_optional && (operand->flags & S390_OPERAND_INDEX))
+ if (omitted_index && (operand->flags & S390_OPERAND_INDEX))
{
/* We do an early skip. For D(X,B) constructions the index
- register is skipped (X is optional). For D(L,B) the base
+ if (operand->flags & S390_OPERAND_VR)
+ as_bad (_("missing vector index register operand"))
register will be the skipped operand, because L is NOT
optional. */
- skip_optional = 0;
+ if (*str == ',')
+ str++;
+ omitted_index = 0;
continue;
}
@@ -1344,5 +1523,7 @@
as_fatal (_("invalid length field specified"));
if ((operand->flags & S390_OPERAND_INDEX)
+ && !(operand->flags & S390_OPERAND_VR)
&& ex.X_add_number == 0
&& warn_areg_zero)
as_warn (_("index register specified but zero"));
@@ -1473,5 +1695,9 @@
then we have a syntax error. */
operand = s390_operands + *(++opindex_ptr);
- if (!(operand->flags & (S390_OPERAND_INDEX|S390_OPERAND_BASE)))
+ if (!(((operand->flags & S390_OPERAND_INDEX) &&
+ !(operand->flags & S390_OPERAND_VR))
+ || (operand->flags & S390_OPERAND_BASE)))
as_bad (_("syntax error; missing '(' after displacement"));
@@ -1509,19 +1743,18 @@
there is a comma right after the opening parentheses,
we have to skip optional operands. */
- if (*f == ',' && f == str)
- {
+ omitted_index = ((*f == ',' && f == str) || (*f == ')'));
/* comma directly after '(' ? */
- skip_optional = 1;
- str++;
- }
- else
- skip_optional = (*f != ',');
}
}
else if (operand->flags & S390_OPERAND_BASE)
{
/* After the base register the parenthesised block ends. */
- if (*str++ != ')')
+ if (*str != ')')
as_bad (_("syntax error; missing ')' after base register"));
- skip_optional = 0;
+ else
+ str++;
+ omitted_index = 0;
@@ -1548,12 +1787,17 @@
{
/* We can find an 'early' closing parentheses in e.g. D(L) instead
of D(L,B). In this case the base register has to be skipped. */
- if (*str == ')')
+ Same if the base register has been explicilty omitted in e.g.
+ if (*str == ')' || (str[0] == ',' && str[1] == ')'))
{
operand = s390_operands + *(++opindex_ptr);
if (!(operand->flags & S390_OPERAND_BASE))
as_bad (_("syntax error; ')' not allowed here"));
+ if (*str == ',')
+ str++;
str++;
}
--
You received this bug notification because you are a member of Ubuntu
Foundations Bugs, which is subscribed to binutils in Ubuntu.
https://bugs.launchpad.net/bugs/2108997
Title:
[SRU] GDB: Internal binutils code requires updates made for IBM z17 in
binutils already
Status in Ubuntu on IBM z Systems:
Fix Committed
Status in binutils package in Ubuntu:
Invalid
Status in binutils source package in Jammy:
Opinion
Status in binutils source package in Noble:
Fix Committed
Status in binutils source package in Oracular:
Won't Fix
Status in binutils source package in Plucky:
Won't Fix
Status in binutils source package in Questing:
Invalid
Bug description:
SRU Justification:
[ Impact ]
* Systems like the new z17 are designed for long running workloads,
hence a non-LTS Ubuntu version is not properly suited for production
workloads, hence users/customers/partners want to use an Ubuntu LTS.
However, 25.04 is the first Ubuntu release that comes with full
support for z17.
* Ubuntu, incl. latest LTS, can already be installed on this hardware,
but only in toleration mode.
But it's important and desired to be able to exploit the latest
hardware generation, means building code for it, but also maintaining
and potentially debugging it.
Hence, the modifications in binutils/gdb
(which is part of a bigger hwe effort).
Without this no proper z17 code life-cycle management (incl. debugging)
is possible and opcodes might be unknown.
* With the above I believe that this corresponds to a hardware
enablement SRU.
* It introduces support for the new IBM z17 hardware to binutils.
* Some Ubuntu releases (like plucky) have already 'anonymous' support
for in terms of 'arch-15', other Ubuntu releases have no 'arch-15' nor
z17 support at all and require two more patches.
* Without this binutils are not aware about the new z17 hardware generation
and it's opcodes etc.
* The intention here is NOT to recompile existing Ubuntu packages
for a new hardware generation (new base-line) as part of this SRU.
It is to enable users to compile their own code and applications
(and debug and maintain it) for and on this new hardware generation.
Being able to exploit this new hardware generation can have
a significant positive performance impact for certain use cases.
[ Fix ]
* eeafc61979c6f8399bb5ce770e46a00823a5cfae ("s390: Make operand table
indices relative to each other") - pre-req. for jammy only
* a3f1e7c56a60573562e8578ae8b675ec1f4448e7 ("s390: Simplify
(dis)assembly of insn operands with const bits") - pre-req. for jammy,
noble and oracular
* a98a6fa2d8ef5eb61534b07db80850dcdf07bdb4 ("s390: Add arch15
instructions") - pre-req. for jammy, noble and oracular
* < 981fe5fd80faf511aa265e841a380c9b46be30e6 ("390: Add support for
z17 as CPU name") >
[ Test Plan ]
* Check if the same (proper) opcodes are detected on an IBM z17
system with and without the patch.
Since the identification and name of a z17 system was added.
* Or the simplest test is probably to check
(after having 'binutils' installed on an
Ubuntu Server 25.04, 24.10 or 24.04 s390x system)
if not only:
'as -m64 -march=arch15 --target-help'
but especially also:
'as -m64 -march=z17 --target-help'
succeeds and leads to the same output.
(As it does for '-march=arch14' and '-march=z16'.)
* Due to the lack of hardware this needs to be tested at IBM.
[ Where problems could occur ]
* The request came in to apply only commit eeafc61979c6.
But this commit alone only applies to plucky as-is.
And in case of plucky I think that the risk for regressions is
relatively moderate, since it mainly adds to the opcodes "z17"
in addition to the already existing "arch15".
* Regressions are still possible, for example if the statements are
not properly expanded with ANDs or ||s, but this is testable
and covered by the test plan.
* On top the new name could be wrong, or the name could be accidentally
mapped to the wrong internal arch.
(The test plan above will allow to identify this and the previous bullet.)
* For oracular (which could probably be skipped now, because we are
very close to it's end of live anyway) and for noble, two more
commits are needed. This definitely increases the potential risk of
regressions.
* But add. commits add the actual "arch15" and it's corresponding code,
before then making "arch15" also known as "z17" (1st commit).
* Commit a98a6fa2d8ef only adds code and opcodes,
hence this will ideally not affect any older hw generations.
* Commit a3f1e7c56a60 however introduces a simplification on how
operands are handled with const bits.
But this is already included in oracular and plucky, so it's there
as well as upstream established and tested.
* In addition all this is limited to the s390x architecture
(except the doc file as/doc/as.texi),
and will cause no harm for any other architecture,
and the request for adding these commits is coming from the
architecture owner.
* Anyway, the majority of risk is in this later commit, and it could
be helpful to mitigate this with further test cases.
* For regression testing:
- doing a (PPA) build (e.g. of the s390-tools package)
on z13 and z15 (that we have direct access to),
using the new binutils version
- verifying and comparing the ddeb packages
- performing a test debug session, verifying that debugging still works
[ Other Info ]
* binutils maintainer (doko) told me that binutils for questing
will be updated anyway to latest release/snapshot,
so nothing to do for questing in this LP bug (and set to Invalid).
* Due to the proximity of oracular's end of life,
the SRU to oracular might be skipped.
* Due to the growing amount of changes that are needed for jammy
I updated the status to 'Opinion'.
__________
With IBM having announced the new IBM z17, Ubuntu 22.04 and 24.04
should be enabled to run properly on the latest s390x hardware.
While plucky has already the required patches included, please
backport to noble and jammy the GNU Binutils mainline commit
981fe5fd80fa ("s390: Add support for z17 as CPU name"), which adds the
real CPU name "z17" as alternative for "arch15".
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