[Bug 2153384] [NEW] Radxa Orion O6N Sleep or suspend, unable to wake up

Alucn 2153384 at bugs.launchpad.net
Wed May 20 02:00:06 UTC 2026 

Public bug reported:

Ubuntu 26.04
I discovered a bug where the keyboard could wake up the monitor after it turned off, but the monitor showed no signal. After multiple attempts, I turned off the monitor's power and turned it back on after a while, only to find that the display was normal and a lock screen appeared.

[  649.100678] wlp97s0: RX AssocResp from 10:04:c1:03:61:37 (capab=0x431 status=0 aid=1)
[  649.208030] wlp97s0: associated
[ 2014.073568] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_encoder_disable][info]enter
[ 2014.073760] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_ctrl_stream_off][info]trilin_dp_encoder_disable stream_id=0, active_stream_cnt=0
[ 2014.077436] linlondp CIXH5010:04: linlondp_crtc_atomic_disable enter
[ 2014.100220] linlondp CIXH5010:04: linlondp_crtc_atomic_disable exit
[ 2014.100233] linlondp CIXH5010:04: linlondp_dev_suspend
[ 2014.100242] [drm] Disconnect mmu without internal TBU!
[ 2034.376114] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_hpd_event_work_func][info]dp hpd event received: Unplugged
[ 2035.192787] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_hpd_event_work_func][info]dp hpd event received: Plugged
[ 2035.257883] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_connector_mode_valid][info]filtered mode(3840x2160 at 1339630) for high pixel rate
[ 2035.257910] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_connector_mode_valid][info]filtered mode(3840x2160 at 1398400) for high pixel rate
[ 2384.004985] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_encoder_compute_config][info]mode 3840x2160 clock=594000 bpc=10 bpp=30 link_rate=810000 (HBR3) lanes=4 max_bpc=10
[ 2384.008908] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_encoder_atomic_mode_set][info]set mode: 3840x2160 594000
[ 2384.008935] linlondp CIXH5010:04: linlondp_crtc_atomic_enable enter
[ 2384.008947] linlondp CIXH5010:04: linlondp_crtc_atomic_enable, succeed to enable aclk.
[ 2384.009459] linlondp CIXH5010:04: linlondp_dev_resume
[ 2384.009477] [drm] Connect mmu without internal TBU!
[ 2384.010165] linlondp CIXH5010:04: linlondp_crtc_atomic_enable exit
[ 2384.010172] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_encoder_enable][info]enter
[ 2384.012566] cix-usbdp-phy CIXH2033:03: sky1_udphy_init: typec dir= 0x0
[ 2384.012832] cix-usbdp-phy CIXH2033:03: sky1_udphy_init: sky1_udphy_dp_conf
[ 2384.013126] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_core_on][info]Successly initialize DP phy
[ 2384.050994] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_core_on][info]main link training done! rate:810000 lanes:4 
[ 2384.051107] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_ctrl_stream_on][info]trilin_dp_encoder_enable stream_id=0, active_stream_cnt:1
[ 2384.932677] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_hpd_event_work_func][info]dp hpd event received: Unplugged
[ 2385.386792] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_hpd_event_work_func][info]dp hpd event received: Plugged
[ 2385.449570] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_connector_mode_valid][info]filtered mode(3840x2160 at 1339630) for high pixel rate
[ 2385.449598] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_connector_mode_valid][info]filtered mode(3840x2160 at 1398400) for high pixel rate
[ 2405.410134] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_hpd_event_work_func][info]dp hpd event received: Unplugged
[ 2406.227139] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_hpd_event_work_func][info]dp hpd event received: Plugged
[ 2406.291524] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_connector_mode_valid][info]filtered mode(3840x2160 at 1339630) for high pixel rate
[ 2406.291551] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_connector_mode_valid][info]filtered mode(3840x2160 at 1398400) for high pixel rate
[ 2475.160528] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_encoder_disable][info]enter
[ 2475.160578] linlondp CIXH5010:04: linlondp_crtc_atomic_disable enter
[ 2475.194116] linlondp CIXH5010:04: linlondp_crtc_atomic_disable exit
[ 2475.194248] linlondp CIXH5010:04: linlondp_dev_suspend
[ 2475.194267] [drm] Disconnect mmu without internal TBU!
[ 2728.760665] hrtimer: interrupt took 10150 ns
[ 3015.193948] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_encoder_compute_config][info]mode 3840x2160 clock=594000 bpc=10 bpp=30 link_rate=810000 (HBR3) lanes=4 max_bpc=10
[ 3015.196876] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_encoder_atomic_mode_set][info]set mode: 3840x2160 594000
[ 3015.196894] linlondp CIXH5010:04: linlondp_crtc_atomic_enable enter
[ 3015.196903] linlondp CIXH5010:04: linlondp_crtc_atomic_enable, succeed to enable aclk.
[ 3015.197309] linlondp CIXH5010:04: linlondp_dev_resume
[ 3015.197323] [drm] Connect mmu without internal TBU!
[ 3015.197649] linlondp CIXH5010:04: linlondp_crtc_atomic_enable exit
[ 3015.197663] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_encoder_enable][info]enter
[ 3015.199946] cix-usbdp-phy CIXH2033:03: sky1_udphy_init: typec dir= 0x0
[ 3015.200078] cix-usbdp-phy CIXH2033:03: sky1_udphy_init: sky1_udphy_dp_conf
[ 3015.200360] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_core_on][info]Successly initialize DP phy
[ 3015.239623] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_core_on][info]main link training done! rate:810000 lanes:4 
[ 3015.239638] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_ctrl_stream_on][info]trilin_dp_encoder_enable stream_id=0, active_stream_cnt:1
[ 3016.118397] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_hpd_event_work_func][info]dp hpd event received: Unplugged
[ 3016.571752] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_hpd_event_work_func][info]dp hpd event received: Plugged
[ 3016.636101] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_connector_mode_valid][info]filtered mode(3840x2160 at 1339630) for high pixel rate
[ 3016.636128] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_connector_mode_valid][info]filtered mode(3840x2160 at 1398400) for high pixel rate
[ 3036.596946] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_hpd_event_work_func][info]dp hpd event received: Unplugged
[ 3037.414017] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_hpd_event_work_func][info]dp hpd event received: Plugged
[ 3037.479133] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_connector_mode_valid][info]filtered mode(3840x2160 at 1339630) for high pixel rate
[ 3037.479161] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_connector_mode_valid][info]filtered mode(3840x2160 at 1398400) for high pixel rate
[ 3064.071566] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_encoder_disable][info]enter
[ 3064.071586] linlondp CIXH5010:04: linlondp_crtc_atomic_disable enter
[ 3064.098187] linlondp CIXH5010:04: linlondp_crtc_atomic_disable exit
[ 3064.098365] linlondp CIXH5010:04: linlondp_dev_suspend
[ 3064.098388] [drm] Disconnect mmu without internal TBU!
[ 3066.935875] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_encoder_compute_config][info]mode 3840x2160 clock=594000 bpc=10 bpp=30 link_rate=810000 (HBR3) lanes=4 max_bpc=10
[ 3066.940218] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_encoder_atomic_mode_set][info]set mode: 3840x2160 594000
[ 3066.940230] linlondp CIXH5010:04: linlondp_crtc_atomic_enable enter
[ 3066.940234] linlondp CIXH5010:04: linlondp_crtc_atomic_enable, succeed to enable aclk.
[ 3066.940405] linlondp CIXH5010:04: linlondp_dev_resume
[ 3066.940414] [drm] Connect mmu without internal TBU!
[ 3066.940609] linlondp CIXH5010:04: linlondp_crtc_atomic_enable exit
[ 3066.940613] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_encoder_enable][info]enter
[ 3066.942874] cix-usbdp-phy CIXH2033:03: sky1_udphy_init: typec dir= 0x0
[ 3066.943053] cix-usbdp-phy CIXH2033:03: sky1_udphy_init: sky1_udphy_dp_conf
[ 3066.943365] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_core_on][info]Successly initialize DP phy
[ 3066.989868] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_core_on][info]main link training done! rate:810000 lanes:4 
[ 3066.989888] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_ctrl_stream_on][info]trilin_dp_encoder_enable stream_id=0, active_stream_cnt:1
[ 3079.529628] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_hpd_event_work_func][info]dp hpd event received: Unplugged
[ 3080.346698] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_hpd_event_work_func][info]dp hpd event received: Plugged
[ 3080.409853] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_connector_mode_valid][info]filtered mode(3840x2160 at 1339630) for high pixel rate
[ 3080.409880] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_connector_mode_valid][info]filtered mode(3840x2160 at 1398400) for high pixel rate
[ 3126.176850] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_encoder_disable][info]enter
[ 3126.176872] linlondp CIXH5010:04: linlondp_crtc_atomic_disable enter
[ 3126.208079] linlondp CIXH5010:04: linlondp_crtc_atomic_disable exit
[ 3126.208099] linlondp CIXH5010:04: linlondp_dev_suspend
[ 3126.208110] [drm] Disconnect mmu without internal TBU!
[ 3289.111643] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_encoder_compute_config][info]mode 3840x2160 clock=594000 bpc=10 bpp=30 link_rate=810000 (HBR3) lanes=4 max_bpc=10
[ 3289.115386] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_encoder_atomic_mode_set][info]set mode: 3840x2160 594000
[ 3289.115406] linlondp CIXH5010:04: linlondp_crtc_atomic_enable enter
[ 3289.115416] linlondp CIXH5010:04: linlondp_crtc_atomic_enable, succeed to enable aclk.
[ 3289.115618] linlondp CIXH5010:04: linlondp_dev_resume
[ 3289.115627] [drm] Connect mmu without internal TBU!
[ 3289.115830] linlondp CIXH5010:04: linlondp_crtc_atomic_enable exit
[ 3289.115834] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_encoder_enable][info]enter
[ 3289.118126] cix-usbdp-phy CIXH2033:03: sky1_udphy_init: typec dir= 0x0
[ 3289.118221] cix-usbdp-phy CIXH2033:03: sky1_udphy_init: sky1_udphy_dp_conf
[ 3289.118503] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_core_on][info]Successly initialize DP phy
[ 3289.156466] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_core_on][info]main link training done! rate:810000 lanes:4 
[ 3289.156490] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_ctrl_stream_on][info]trilin_dp_encoder_enable stream_id=0, active_stream_cnt:1
[ 3290.070488] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_hpd_event_work_func][info]dp hpd event received: Unplugged
[ 3290.524553] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_hpd_event_work_func][info]dp hpd event received: Plugged
[ 3290.590555] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_connector_mode_valid][info]filtered mode(3840x2160 at 1339630) for high pixel rate
[ 3290.590592] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_connector_mode_valid][info]filtered mode(3840x2160 at 1398400) for high pixel rate
[ 3310.547905] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_hpd_event_work_func][info]dp hpd event received: Unplugged
[ 3311.364887] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_hpd_event_work_func][info]dp hpd event received: Plugged
[ 3311.430012] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_connector_mode_valid][info]filtered mode(3840x2160 at 1339630) for high pixel rate
[ 3311.430039] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_connector_mode_valid][info]filtered mode(3840x2160 at 1398400) for high pixel rate
[ 3357.298789] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_encoder_disable][info]enter
[ 3357.298836] linlondp CIXH5010:04: linlondp_crtc_atomic_disable enter
[ 3357.316809] linlondp CIXH5010:04: linlondp_crtc_atomic_disable exit
[ 3357.316898] linlondp CIXH5010:04: linlondp_dev_suspend
[ 3357.316909] [drm] Disconnect mmu without internal TBU!
[ 3358.461218] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_encoder_compute_config][info]mode 3840x2160 clock=594000 bpc=10 bpp=30 link_rate=810000 (HBR3) lanes=4 max_bpc=10
[ 3358.462708] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_encoder_atomic_mode_set][info]set mode: 3840x2160 594000
[ 3358.462741] linlondp CIXH5010:04: linlondp_crtc_atomic_enable enter
[ 3358.462759] linlondp CIXH5010:04: linlondp_crtc_atomic_enable, succeed to enable aclk.
[ 3358.463610] linlondp CIXH5010:04: linlondp_dev_resume
[ 3358.463638] [drm] Connect mmu without internal TBU!
[ 3358.464224] linlondp CIXH5010:04: linlondp_crtc_atomic_enable exit
[ 3358.464248] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_encoder_enable][info]enter
[ 3358.466644] cix-usbdp-phy CIXH2033:03: sky1_udphy_init: typec dir= 0x0
[ 3358.466895] cix-usbdp-phy CIXH2033:03: sky1_udphy_init: sky1_udphy_dp_conf
[ 3358.467229] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_core_on][info]Successly initialize DP phy
[ 3358.506923] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_core_on][info]main link training done! rate:810000 lanes:4 
[ 3358.506966] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_ctrl_stream_on][info]trilin_dp_encoder_enable stream_id=0, active_stream_cnt:1
[ 3359.410893] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_hpd_event_work_func][info]dp hpd event received: Unplugged
[ 3359.864905] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_hpd_event_work_func][info]dp hpd event received: Plugged
[ 3359.933423] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_connector_mode_valid][info]filtered mode(3840x2160 at 1339630) for high pixel rate
[ 3359.933489] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_connector_mode_valid][info]filtered mode(3840x2160 at 1398400) for high pixel rate
[ 3379.888336] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_hpd_event_work_func][info]dp hpd event received: Unplugged
[ 3380.705383] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_hpd_event_work_func][info]dp hpd event received: Plugged
[ 3380.771415] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_connector_mode_valid][info]filtered mode(3840x2160 at 1339630) for high pixel rate
[ 3380.771442] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_connector_mode_valid][info]filtered mode(3840x2160 at 1398400) for high pixel rate
[ 3396.049248] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_hpd_event_work_func][info]dp hpd event received: Unplugged
[ 3399.825961] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_encoder_disable][info]enter
[ 3399.826006] linlondp CIXH5010:04: linlondp_crtc_atomic_disable enter
[ 3399.848303] linlondp CIXH5010:04: linlondp_crtc_atomic_disable exit
[ 3399.848399] linlondp CIXH5010:04: linlondp_dev_suspend
[ 3399.848410] [drm] Disconnect mmu without internal TBU!
[ 3652.748430] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_hpd_event_work_func][info]dp hpd event received: Plugged
[ 3652.840751] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_connector_mode_valid][info]filtered mode(3840x2160 at 1339630) for high pixel rate
[ 3652.840781] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_connector_mode_valid][info]filtered mode(3840x2160 at 1398400) for high pixel rate
[ 3654.643523] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_encoder_compute_config][info]mode 3840x2160 clock=594000 bpc=10 bpp=30 link_rate=810000 (HBR3) lanes=4 max_bpc=10
[ 3654.643601] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_encoder_atomic_mode_set][info]set mode: 3840x2160 594000
[ 3654.643612] linlondp CIXH5010:04: linlondp_crtc_atomic_enable enter
[ 3654.643620] linlondp CIXH5010:04: linlondp_crtc_atomic_enable, succeed to enable aclk.
[ 3654.643940] linlondp CIXH5010:04: linlondp_dev_resume
[ 3654.643952] [drm] Connect mmu without internal TBU!
[ 3654.644509] linlondp CIXH5010:04: linlondp_crtc_atomic_enable exit
[ 3654.644535] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_encoder_enable][info]enter
[ 3654.646956] cix-usbdp-phy CIXH2033:03: sky1_udphy_init: typec dir= 0x0
[ 3654.647151] cix-usbdp-phy CIXH2033:03: sky1_udphy_init: sky1_udphy_dp_conf
[ 3654.647459] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_core_on][info]Successly initialize DP phy
[ 3654.697934] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_core_on][info]main link training done! rate:810000 lanes:4 
[ 3654.697984] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_ctrl_stream_on][info]trilin_dp_encoder_enable stream_id=0, active_stream_cnt:1

** Affects: ubuntu-concept
     Importance: Undecided
         Status: New

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https://bugs.launchpad.net/bugs/2153384

Title:
  Radxa Orion O6N Sleep or suspend, unable to wake up

Status in ubuntu-concept:
  New

Bug description:
  Ubuntu 26.04
  I discovered a bug where the keyboard could wake up the monitor after it turned off, but the monitor showed no signal. After multiple attempts, I turned off the monitor's power and turned it back on after a while, only to find that the display was normal and a lock screen appeared.

  [  649.100678] wlp97s0: RX AssocResp from 10:04:c1:03:61:37 (capab=0x431 status=0 aid=1)
  [  649.208030] wlp97s0: associated
  [ 2014.073568] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_encoder_disable][info]enter
  [ 2014.073760] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_ctrl_stream_off][info]trilin_dp_encoder_disable stream_id=0, active_stream_cnt=0
  [ 2014.077436] linlondp CIXH5010:04: linlondp_crtc_atomic_disable enter
  [ 2014.100220] linlondp CIXH5010:04: linlondp_crtc_atomic_disable exit
  [ 2014.100233] linlondp CIXH5010:04: linlondp_dev_suspend
  [ 2014.100242] [drm] Disconnect mmu without internal TBU!
  [ 2034.376114] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_hpd_event_work_func][info]dp hpd event received: Unplugged
  [ 2035.192787] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_hpd_event_work_func][info]dp hpd event received: Plugged
  [ 2035.257883] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_connector_mode_valid][info]filtered mode(3840x2160 at 1339630) for high pixel rate
  [ 2035.257910] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_connector_mode_valid][info]filtered mode(3840x2160 at 1398400) for high pixel rate
  [ 2384.004985] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_encoder_compute_config][info]mode 3840x2160 clock=594000 bpc=10 bpp=30 link_rate=810000 (HBR3) lanes=4 max_bpc=10
  [ 2384.008908] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_encoder_atomic_mode_set][info]set mode: 3840x2160 594000
  [ 2384.008935] linlondp CIXH5010:04: linlondp_crtc_atomic_enable enter
  [ 2384.008947] linlondp CIXH5010:04: linlondp_crtc_atomic_enable, succeed to enable aclk.
  [ 2384.009459] linlondp CIXH5010:04: linlondp_dev_resume
  [ 2384.009477] [drm] Connect mmu without internal TBU!
  [ 2384.010165] linlondp CIXH5010:04: linlondp_crtc_atomic_enable exit
  [ 2384.010172] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_encoder_enable][info]enter
  [ 2384.012566] cix-usbdp-phy CIXH2033:03: sky1_udphy_init: typec dir= 0x0
  [ 2384.012832] cix-usbdp-phy CIXH2033:03: sky1_udphy_init: sky1_udphy_dp_conf
  [ 2384.013126] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_core_on][info]Successly initialize DP phy
  [ 2384.050994] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_core_on][info]main link training done! rate:810000 lanes:4 
  [ 2384.051107] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_ctrl_stream_on][info]trilin_dp_encoder_enable stream_id=0, active_stream_cnt:1
  [ 2384.932677] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_hpd_event_work_func][info]dp hpd event received: Unplugged
  [ 2385.386792] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_hpd_event_work_func][info]dp hpd event received: Plugged
  [ 2385.449570] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_connector_mode_valid][info]filtered mode(3840x2160 at 1339630) for high pixel rate
  [ 2385.449598] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_connector_mode_valid][info]filtered mode(3840x2160 at 1398400) for high pixel rate
  [ 2405.410134] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_hpd_event_work_func][info]dp hpd event received: Unplugged
  [ 2406.227139] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_hpd_event_work_func][info]dp hpd event received: Plugged
  [ 2406.291524] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_connector_mode_valid][info]filtered mode(3840x2160 at 1339630) for high pixel rate
  [ 2406.291551] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_connector_mode_valid][info]filtered mode(3840x2160 at 1398400) for high pixel rate
  [ 2475.160528] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_encoder_disable][info]enter
  [ 2475.160578] linlondp CIXH5010:04: linlondp_crtc_atomic_disable enter
  [ 2475.194116] linlondp CIXH5010:04: linlondp_crtc_atomic_disable exit
  [ 2475.194248] linlondp CIXH5010:04: linlondp_dev_suspend
  [ 2475.194267] [drm] Disconnect mmu without internal TBU!
  [ 2728.760665] hrtimer: interrupt took 10150 ns
  [ 3015.193948] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_encoder_compute_config][info]mode 3840x2160 clock=594000 bpc=10 bpp=30 link_rate=810000 (HBR3) lanes=4 max_bpc=10
  [ 3015.196876] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_encoder_atomic_mode_set][info]set mode: 3840x2160 594000
  [ 3015.196894] linlondp CIXH5010:04: linlondp_crtc_atomic_enable enter
  [ 3015.196903] linlondp CIXH5010:04: linlondp_crtc_atomic_enable, succeed to enable aclk.
  [ 3015.197309] linlondp CIXH5010:04: linlondp_dev_resume
  [ 3015.197323] [drm] Connect mmu without internal TBU!
  [ 3015.197649] linlondp CIXH5010:04: linlondp_crtc_atomic_enable exit
  [ 3015.197663] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_encoder_enable][info]enter
  [ 3015.199946] cix-usbdp-phy CIXH2033:03: sky1_udphy_init: typec dir= 0x0
  [ 3015.200078] cix-usbdp-phy CIXH2033:03: sky1_udphy_init: sky1_udphy_dp_conf
  [ 3015.200360] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_core_on][info]Successly initialize DP phy
  [ 3015.239623] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_core_on][info]main link training done! rate:810000 lanes:4 
  [ 3015.239638] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_ctrl_stream_on][info]trilin_dp_encoder_enable stream_id=0, active_stream_cnt:1
  [ 3016.118397] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_hpd_event_work_func][info]dp hpd event received: Unplugged
  [ 3016.571752] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_hpd_event_work_func][info]dp hpd event received: Plugged
  [ 3016.636101] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_connector_mode_valid][info]filtered mode(3840x2160 at 1339630) for high pixel rate
  [ 3016.636128] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_connector_mode_valid][info]filtered mode(3840x2160 at 1398400) for high pixel rate
  [ 3036.596946] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_hpd_event_work_func][info]dp hpd event received: Unplugged
  [ 3037.414017] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_hpd_event_work_func][info]dp hpd event received: Plugged
  [ 3037.479133] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_connector_mode_valid][info]filtered mode(3840x2160 at 1339630) for high pixel rate
  [ 3037.479161] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_connector_mode_valid][info]filtered mode(3840x2160 at 1398400) for high pixel rate
  [ 3064.071566] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_encoder_disable][info]enter
  [ 3064.071586] linlondp CIXH5010:04: linlondp_crtc_atomic_disable enter
  [ 3064.098187] linlondp CIXH5010:04: linlondp_crtc_atomic_disable exit
  [ 3064.098365] linlondp CIXH5010:04: linlondp_dev_suspend
  [ 3064.098388] [drm] Disconnect mmu without internal TBU!
  [ 3066.935875] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_encoder_compute_config][info]mode 3840x2160 clock=594000 bpc=10 bpp=30 link_rate=810000 (HBR3) lanes=4 max_bpc=10
  [ 3066.940218] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_encoder_atomic_mode_set][info]set mode: 3840x2160 594000
  [ 3066.940230] linlondp CIXH5010:04: linlondp_crtc_atomic_enable enter
  [ 3066.940234] linlondp CIXH5010:04: linlondp_crtc_atomic_enable, succeed to enable aclk.
  [ 3066.940405] linlondp CIXH5010:04: linlondp_dev_resume
  [ 3066.940414] [drm] Connect mmu without internal TBU!
  [ 3066.940609] linlondp CIXH5010:04: linlondp_crtc_atomic_enable exit
  [ 3066.940613] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_encoder_enable][info]enter
  [ 3066.942874] cix-usbdp-phy CIXH2033:03: sky1_udphy_init: typec dir= 0x0
  [ 3066.943053] cix-usbdp-phy CIXH2033:03: sky1_udphy_init: sky1_udphy_dp_conf
  [ 3066.943365] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_core_on][info]Successly initialize DP phy
  [ 3066.989868] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_core_on][info]main link training done! rate:810000 lanes:4 
  [ 3066.989888] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_ctrl_stream_on][info]trilin_dp_encoder_enable stream_id=0, active_stream_cnt:1
  [ 3079.529628] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_hpd_event_work_func][info]dp hpd event received: Unplugged
  [ 3080.346698] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_hpd_event_work_func][info]dp hpd event received: Plugged
  [ 3080.409853] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_connector_mode_valid][info]filtered mode(3840x2160 at 1339630) for high pixel rate
  [ 3080.409880] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_connector_mode_valid][info]filtered mode(3840x2160 at 1398400) for high pixel rate
  [ 3126.176850] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_encoder_disable][info]enter
  [ 3126.176872] linlondp CIXH5010:04: linlondp_crtc_atomic_disable enter
  [ 3126.208079] linlondp CIXH5010:04: linlondp_crtc_atomic_disable exit
  [ 3126.208099] linlondp CIXH5010:04: linlondp_dev_suspend
  [ 3126.208110] [drm] Disconnect mmu without internal TBU!
  [ 3289.111643] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_encoder_compute_config][info]mode 3840x2160 clock=594000 bpc=10 bpp=30 link_rate=810000 (HBR3) lanes=4 max_bpc=10
  [ 3289.115386] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_encoder_atomic_mode_set][info]set mode: 3840x2160 594000
  [ 3289.115406] linlondp CIXH5010:04: linlondp_crtc_atomic_enable enter
  [ 3289.115416] linlondp CIXH5010:04: linlondp_crtc_atomic_enable, succeed to enable aclk.
  [ 3289.115618] linlondp CIXH5010:04: linlondp_dev_resume
  [ 3289.115627] [drm] Connect mmu without internal TBU!
  [ 3289.115830] linlondp CIXH5010:04: linlondp_crtc_atomic_enable exit
  [ 3289.115834] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_encoder_enable][info]enter
  [ 3289.118126] cix-usbdp-phy CIXH2033:03: sky1_udphy_init: typec dir= 0x0
  [ 3289.118221] cix-usbdp-phy CIXH2033:03: sky1_udphy_init: sky1_udphy_dp_conf
  [ 3289.118503] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_core_on][info]Successly initialize DP phy
  [ 3289.156466] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_core_on][info]main link training done! rate:810000 lanes:4 
  [ 3289.156490] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_ctrl_stream_on][info]trilin_dp_encoder_enable stream_id=0, active_stream_cnt:1
  [ 3290.070488] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_hpd_event_work_func][info]dp hpd event received: Unplugged
  [ 3290.524553] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_hpd_event_work_func][info]dp hpd event received: Plugged
  [ 3290.590555] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_connector_mode_valid][info]filtered mode(3840x2160 at 1339630) for high pixel rate
  [ 3290.590592] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_connector_mode_valid][info]filtered mode(3840x2160 at 1398400) for high pixel rate
  [ 3310.547905] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_hpd_event_work_func][info]dp hpd event received: Unplugged
  [ 3311.364887] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_hpd_event_work_func][info]dp hpd event received: Plugged
  [ 3311.430012] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_connector_mode_valid][info]filtered mode(3840x2160 at 1339630) for high pixel rate
  [ 3311.430039] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_connector_mode_valid][info]filtered mode(3840x2160 at 1398400) for high pixel rate
  [ 3357.298789] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_encoder_disable][info]enter
  [ 3357.298836] linlondp CIXH5010:04: linlondp_crtc_atomic_disable enter
  [ 3357.316809] linlondp CIXH5010:04: linlondp_crtc_atomic_disable exit
  [ 3357.316898] linlondp CIXH5010:04: linlondp_dev_suspend
  [ 3357.316909] [drm] Disconnect mmu without internal TBU!
  [ 3358.461218] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_encoder_compute_config][info]mode 3840x2160 clock=594000 bpc=10 bpp=30 link_rate=810000 (HBR3) lanes=4 max_bpc=10
  [ 3358.462708] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_encoder_atomic_mode_set][info]set mode: 3840x2160 594000
  [ 3358.462741] linlondp CIXH5010:04: linlondp_crtc_atomic_enable enter
  [ 3358.462759] linlondp CIXH5010:04: linlondp_crtc_atomic_enable, succeed to enable aclk.
  [ 3358.463610] linlondp CIXH5010:04: linlondp_dev_resume
  [ 3358.463638] [drm] Connect mmu without internal TBU!
  [ 3358.464224] linlondp CIXH5010:04: linlondp_crtc_atomic_enable exit
  [ 3358.464248] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_encoder_enable][info]enter
  [ 3358.466644] cix-usbdp-phy CIXH2033:03: sky1_udphy_init: typec dir= 0x0
  [ 3358.466895] cix-usbdp-phy CIXH2033:03: sky1_udphy_init: sky1_udphy_dp_conf
  [ 3358.467229] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_core_on][info]Successly initialize DP phy
  [ 3358.506923] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_core_on][info]main link training done! rate:810000 lanes:4 
  [ 3358.506966] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_ctrl_stream_on][info]trilin_dp_encoder_enable stream_id=0, active_stream_cnt:1
  [ 3359.410893] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_hpd_event_work_func][info]dp hpd event received: Unplugged
  [ 3359.864905] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_hpd_event_work_func][info]dp hpd event received: Plugged
  [ 3359.933423] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_connector_mode_valid][info]filtered mode(3840x2160 at 1339630) for high pixel rate
  [ 3359.933489] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_connector_mode_valid][info]filtered mode(3840x2160 at 1398400) for high pixel rate
  [ 3379.888336] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_hpd_event_work_func][info]dp hpd event received: Unplugged
  [ 3380.705383] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_hpd_event_work_func][info]dp hpd event received: Plugged
  [ 3380.771415] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_connector_mode_valid][info]filtered mode(3840x2160 at 1339630) for high pixel rate
  [ 3380.771442] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_connector_mode_valid][info]filtered mode(3840x2160 at 1398400) for high pixel rate
  [ 3396.049248] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_hpd_event_work_func][info]dp hpd event received: Unplugged
  [ 3399.825961] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_encoder_disable][info]enter
  [ 3399.826006] linlondp CIXH5010:04: linlondp_crtc_atomic_disable enter
  [ 3399.848303] linlondp CIXH5010:04: linlondp_crtc_atomic_disable exit
  [ 3399.848399] linlondp CIXH5010:04: linlondp_dev_suspend
  [ 3399.848410] [drm] Disconnect mmu without internal TBU!
  [ 3652.748430] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_hpd_event_work_func][info]dp hpd event received: Plugged
  [ 3652.840751] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_connector_mode_valid][info]filtered mode(3840x2160 at 1339630) for high pixel rate
  [ 3652.840781] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_connector_mode_valid][info]filtered mode(3840x2160 at 1398400) for high pixel rate
  [ 3654.643523] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_encoder_compute_config][info]mode 3840x2160 clock=594000 bpc=10 bpp=30 link_rate=810000 (HBR3) lanes=4 max_bpc=10
  [ 3654.643601] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_encoder_atomic_mode_set][info]set mode: 3840x2160 594000
  [ 3654.643612] linlondp CIXH5010:04: linlondp_crtc_atomic_enable enter
  [ 3654.643620] linlondp CIXH5010:04: linlondp_crtc_atomic_enable, succeed to enable aclk.
  [ 3654.643940] linlondp CIXH5010:04: linlondp_dev_resume
  [ 3654.643952] [drm] Connect mmu without internal TBU!
  [ 3654.644509] linlondp CIXH5010:04: linlondp_crtc_atomic_enable exit
  [ 3654.644535] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_encoder_enable][info]enter
  [ 3654.646956] cix-usbdp-phy CIXH2033:03: sky1_udphy_init: typec dir= 0x0
  [ 3654.647151] cix-usbdp-phy CIXH2033:03: sky1_udphy_init: sky1_udphy_dp_conf
  [ 3654.647459] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_core_on][info]Successly initialize DP phy
  [ 3654.697934] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_core_on][info]main link training done! rate:810000 lanes:4 
  [ 3654.697984] trilin-dptx-cix CIXH502F:04: [drm:trilin_dp_ctrl_stream_on][info]trilin_dp_encoder_enable stream_id=0, active_stream_cnt:1

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