[PATCH 1/2] acpi/iort: permit SMMU model values of 4 and 5

[Ard Biesheuvel]

The IORT spec was updated at some point to add support for some
additional SMMU v1/v2 implementations, i.e., the ARM MMU-401 and
the Cavium ThunderX SMMU. So permit these in the validation test.

Signed-off-by: Ard Biesheuvel <ard.biesheuvel at linaro.org>
---
 src/acpi/iort/iort.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/acpi/iort/iort.c b/src/acpi/iort/iort.c
index 16d3b990c342..5e46fabbfccb 100644
--- a/src/acpi/iort/iort.c
+++ b/src/acpi/iort/iort.c
@@ -555,12 +555,12 @@ static void iort_check_smmu(
 		node->pmu_interrupt_array_offset, node->pmu_interrupt_count, passed);
 	iort_id_mappings_check(fw, data, node_end, passed);
 
-	if (node->model > 3) {
+	if (node->model > 5) {
 		*passed = false;
 		fwts_failed(fw, LOG_LEVEL_HIGH,
 			"IORTSmmuInvalidModel",
 			"IORT SMMU Model is 0x%" PRIx32 " and was expecting "
-			"a model value 0 to 3.", node->model);
+			"a model value 0 to 5.", node->model);
 	}
 
 	fwts_acpi_reserved_bits_check(fw, "IORT", "SMMU Reserved Flags", node->flags, sizeof(node->flags), 2, 31, passed);
-- 
2.20.1