[PATCH 3/9] PM - ddr DFS: Fixed MC paramters and DFS flow in SRAM
Brad Figg
brad.figg at canonical.com
Wed Aug 19 03:44:08 UTC 2009
From: Tawfik Bayouk <tawfik at marvell.com>
Signed-off-by: Tawfik Bayouk <tawfik at marvell.com>
Signed-off-by: Saeed Bishara <saeed at marvell.com>
Signed-off-by: Brad Figg <brad.figg at canonical.com>
---
arch/arm/mach-dove/pm.c | 2 +-
.../mv_hal_drivers/mv_hal/ddr/ddrmc/mvDramTmng.c | 19 +++-
.../plat-orion/mv_hal_drivers/mv_hal/pmu/mvPmu.c | 13 ++-
.../mv_hal_drivers/mv_hal/pmu/mvPmu_asm.S | 97 +++++++++++++++-----
4 files changed, 99 insertions(+), 32 deletions(-)
diff --git a/arch/arm/mach-dove/pm.c b/arch/arm/mach-dove/pm.c
index 487e72b..891f933 100755
--- a/arch/arm/mach-dove/pm.c
+++ b/arch/arm/mach-dove/pm.c
@@ -257,7 +257,7 @@ int pmu_proc_write(struct file *file, const char *buffer,unsigned long count,
printk("Set New System Frequencies to CPU %dMhz, L2 %dMhz, DDR %dMhz", cpuFreq, l2Freq, ddrFreq);
local_irq_save(ints);
- mc = MV_REG_READ(CPU_MAIN_INT_CAUSE_HIGH_REG);
+ mc = MV_REG_READ(CPU_MAIN_IRQ_MASK_HIGH_REG);
MV_REG_WRITE(CPU_MAIN_IRQ_MASK_HIGH_REG, (mc | 0x2)); /* PMU Interrupt Enable */
if (mvPmuSysFreqScale (ddrFreq, l2Freq, cpuFreq) != MV_OK)
printk(">>>>>> FAILED\n");
diff --git a/arch/arm/plat-orion/mv_hal_drivers/mv_hal/ddr/ddrmc/mvDramTmng.c b/arch/arm/plat-orion/mv_hal_drivers/mv_hal/ddr/ddrmc/mvDramTmng.c
index 4474ace..2be003a 100755
--- a/arch/arm/plat-orion/mv_hal_drivers/mv_hal/ddr/ddrmc/mvDramTmng.c
+++ b/arch/arm/plat-orion/mv_hal_drivers/mv_hal/ddr/ddrmc/mvDramTmng.c
@@ -152,6 +152,9 @@ MV_U32 mvDramIfParamCountGet(MV_VOID)
else
cnt += MV_DRAM_RECONFIG_CNT;
+ /* Add 1 entry for the DLL reset clearing in DDR reconfig */
+ cnt++;
+
return cnt;
}
@@ -254,7 +257,8 @@ MV_STATUS mvDramIfParamFill(MV_U32 ddrFreq, MV_DDR_MC_PARAMS * params, MV_U32 *
*******************************************************************************/
MV_STATUS mvDramReconfigParamFill(MV_U32 ddrFreq, MV_U32 cpuFreq, MV_DDR_MC_PARAMS * params, MV_U32 * paramcnt)
{
- MV_U32 reg_index, i, mask;
+ MV_U32 reg_index, i, mask;
+ MV_U32 dll_rst = 0;
/* Check that the Uboot passed valid parameters in the TAG */
if (!mv_dram_init_valid) {
@@ -297,6 +301,11 @@ MV_STATUS mvDramReconfigParamFill(MV_U32 ddrFreq, MV_U32 cpuFreq, MV_DDR_MC_PARA
for (i=0; i<*paramcnt; i++) {
params->addr = (mv_dram_init_info.reg_init[reg_index].reg_addr & 0xFFFFF); /* offset only */
params->val = mv_dram_init_info.reg_init[reg_index].reg_value;
+ if (params->addr == 0x80)
+ {
+ dll_rst = params->val;
+ params->val |= 0x40; /* Add DLL reset */
+ }
reg_index++;
params++;
}
@@ -308,8 +317,12 @@ MV_STATUS mvDramReconfigParamFill(MV_U32 ddrFreq, MV_U32 cpuFreq, MV_DDR_MC_PARA
params++;
}
- /* Add the count of LMR and LEMR registers count */
- *paramcnt += MV_DRAM_RECONFIG_CNT;
+ /* Add the DLL reset deasser */
+ params->addr = 0x80;
+ params->val = dll_rst;
+
+ /* Add the count of LMR and LEMR registers count + DLL reset clearing */
+ *paramcnt += (MV_DRAM_RECONFIG_CNT + 1);
return MV_OK;
}
diff --git a/arch/arm/plat-orion/mv_hal_drivers/mv_hal/pmu/mvPmu.c b/arch/arm/plat-orion/mv_hal_drivers/mv_hal/pmu/mvPmu.c
index 2c37baa..378c205 100755
--- a/arch/arm/plat-orion/mv_hal_drivers/mv_hal/pmu/mvPmu.c
+++ b/arch/arm/plat-orion/mv_hal_drivers/mv_hal/pmu/mvPmu.c
@@ -780,6 +780,7 @@ MV_STATUS mvPmuCpuFreqScale (MV_PMU_CPU_SPEED cpuSpeed)
MV_STATUS mvPmuSysFreqScale (MV_U32 ddrFreq, MV_U32 l2Freq, MV_U32 cpuFreq)
{
MV_U32 reg, pllFreq, ddrDiv, l2Div, ddrParamCnt;
+ MV_STATUS ret = MV_OK;
/* Get current PLL frequency */
pllFreq = mvPmuGetPllFreq();
@@ -826,7 +827,7 @@ MV_STATUS mvPmuSysFreqScale (MV_U32 ddrFreq, MV_U32 l2Freq, MV_U32 cpuFreq)
/* Check and clear the DFSDone interrupt */
reg = MV_REG_READ(PMU_INT_CAUSE_REG);
if ((reg & PMU_INT_DFS_DONE_MASK) == 0)
- return MV_FAIL;
+ ret = MV_FAIL;
reg &= ~PMU_INT_DFS_DONE_MASK;
MV_REG_WRITE(PMU_INT_CAUSE_REG, reg);
@@ -839,10 +840,16 @@ MV_STATUS mvPmuSysFreqScale (MV_U32 ddrFreq, MV_U32 l2Freq, MV_U32 cpuFreq)
reg = MV_REG_READ(PMU_DFS_STATUS_REG);
reg = ((reg & PMU_DFS_STAT_DDR_RATIO_MASK) >> PMU_DFS_STAT_DDR_RATIO_OFFS);
if (reg != ddrDiv)
- return MV_OK;
+ ret = MV_FAIL;
/* IRQ and FIQ are unmasked by the PMU */
- return MV_OK;
+#if 0
+ reg = MV_REG_READ(PMU_CTRL_REG);
+ reg &= ~(PMU_CTRL_MASK_IRQ_MASK | PMU_CTRL_MASK_FIQ_MASK);
+ MV_REG_WRITE(PMU_CTRL_REG, reg);
+#endif
+
+ return ret;
}
/*******************************************************************************
diff --git a/arch/arm/plat-orion/mv_hal_drivers/mv_hal/pmu/mvPmu_asm.S b/arch/arm/plat-orion/mv_hal_drivers/mv_hal/pmu/mvPmu_asm.S
index 2c68703..69a9a54 100755
--- a/arch/arm/plat-orion/mv_hal_drivers/mv_hal/pmu/mvPmu_asm.S
+++ b/arch/arm/plat-orion/mv_hal_drivers/mv_hal/pmu/mvPmu_asm.S
@@ -92,17 +92,33 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
ENTRY(mvPmuSramDdrReconfigFunc)
stmfd sp!, {r4 - r10, lr} @ save registers on stack
+ mov r9, r0
+ mov r10, r1
+
/*
* Block all data requests to the MC from the SB
*/
- ldr r2, pmu_ddrfs_mc_ctrl_reg
+ ldr r2, ddfs_mc_ctrl_reg
mov r3, #0x1
str r3, [r2]
+
+ /*
+ * Disable All SB access ro DDR
+ */
+/*
+ ldr r3, ddfs_arbit_val
+ ldr r2, ddfs_arbit_low_reg
+ ldr r7, [r2] @ r7 saves Arbitor HI
+ str r3, [r2]
+ ldr r2, ddfs_arbit_hi_reg
+ ldr r8, [r2] @ r8 saves Arbitor LOW
+ str r3, [r2]
+*/
/*
* Set DDR in Self refresh mode and poll status bit
*/
- ldr r2, pmu_ddrfs_ctrl_reg
+ ldr r2, ddfs_ctrl_reg
mov r3, #PMU_CTRL_MC_SR_REQ_MASK
ldr r4, [r2]
orr r4, r4, r3
@@ -113,30 +129,16 @@ ddr_fs_sr_loop:
beq ddr_fs_sr_loop
/*
- * Loop and execute MC init addr/value couples
- */
-mc_init_loop:
- cmp r1, #0
- beq mc_init_done
- ldr r2, [r0]
- add r0, #4
- ldr r3, [r0]
- add r0, #4
- str r3, [r2]
- sub r1, r1, #1
- b mc_init_loop
-mc_init_done:
-
- /*
* Enter WFI
*/
mov r0, #0
mcr p15, 0, r0, c7, c0, 4
+
/*
* Exit DDR self refresh mode if active
*/
- ldr r0, pmu_ddrfs_ctrl_reg
+ ldr r0, ddfs_ctrl_reg
mov r1, #PMU_CTRL_MC_SR_REQ_MASK
ldr r2, [r0]
tst r2, #PMU_CTRL_MC_SR_REQ_MASK
@@ -150,17 +152,31 @@ ddrfs_sr_exit_loop:
skip_ddrfs_sr_exit:
/*
- * UN-Block data requests to the MC from the SB
+ * Loop and execute MC init addr/value couples
*/
- ldr r2, pmu_ddrfs_mc_ctrl_reg
- mov r3, #0x0
- str r3, [r2]
+ mov r0, r9
+ mov r1, r10
+ ldr r4, ddfs_nb_offset
+ ldr r5, ddfs_nb_mask
+mc_init_loop:
+ cmp r1, #0
+ beq mc_init_done
+ ldr r2, [r0] @ Address
+ add r0, #4
+ ldr r3, [r0] @ Value
+ add r0, #4
+ bic r2, r2, r5
+ orr r2, r2, r4 @ NB Offset
+ str r3, [r2] @ [Address]=Value
+ sub r1, r1, #1
+ b mc_init_loop
+mc_init_done:
/*************************************************************/
/* FOR DEBUG ONLY - BLINK LED ON MPP7 AS A LIFE INDICATION */
/*************************************************************/
/*
- mov r4, #1
+ mov r4, #8
ldr r0, led_addr
ldr r1, led_val_on
ldr r2, led_val_off
@@ -186,19 +202,50 @@ loop_delay2:
*/
/********************************************************************/
+ /*
+ * UN-Block data requests to the MC from the SB
+ */
+ ldr r2, ddfs_mc_ctrl_reg
+ mov r3, #0x0
+ str r3, [r2]
+
+
+ /*
+ * Restore SB access ro DDR
+ */
+/*
+ ldr r2, ddfs_arbit_low_reg
+ str r7, [r2] @ restore Arbitor HI
+ ldr r2, ddfs_arbit_hi_reg
+ str r8, [r2] @ restore Arbitor LOW
+*/
ldmfd sp!, {r4 - r10, pc} @ restore regs and return
-pmu_ddrfs_mc_ctrl_reg:
+ddfs_nb_offset:
+ .word (DOVE_NB_REGS_VIRT_BASE)
+ddfs_nb_mask:
+ .word (0xFFF00000)
+ddfs_mc_ctrl_reg:
.word (DOVE_NB_REGS_VIRT_BASE + 0x7E0)
-pmu_ddrfs_ctrl_reg:
+ddfs_ctrl_reg:
.word (DOVE_SB_REGS_VIRT_BASE + PMU_CTRL_REG)
+/*
+ddfs_arbit_low_reg:
+ .word(DOVE_SB_REGS_VIRT_BASE + 0xD02A8)
+ddfs_arbit_hi_reg:
+ .word(DOVE_SB_REGS_VIRT_BASE + 0xD02AC)
+ddfs_arbit_val:
+ .word(0xFFFFFFFF)
+*/
/*********************************************************************/
+/*
led_addr:
.word (DOVE_SB_REGS_VIRT_BASE + PMU_SIG_SLCT_CTRL_0_REG)
led_val_on:
.word (0x1048B500)
led_val_off:
.word (0x2048B500)
+*/
/*********************************************************************/
ENTRY(mvPmuSramDdrReconfigFuncSZ)
.word . - mvPmuSramDdrReconfigFunc
--
1.6.0.4
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