[PATCH 48/133] [Jaunty SRU] ARM.imx51 Freescale:ENGR00109543 Sets mc13892 CHRGRAW scaling to divide by 5

[Brad Figg]

From: Zhou Jingyu <b02241 at freescale.com>

Sets CHRGRAW scaling to divide by 5

Signed-off-by: Zhou Jingyu <Jingyu.Zhou at freescale.com>
(cherry picked from commit 8702e52d0f7f2a480e27ed27b71ee4be285d867b)
Signed-off-by: Brad Figg <brad.figg at canonical.com>
---
 drivers/mxc/pmic/mc13892/pmic_adc.c |    5 +++--
 1 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/mxc/pmic/mc13892/pmic_adc.c b/drivers/mxc/pmic/mc13892/pmic_adc.c
index 737a99f..eb05c78 100644
--- a/drivers/mxc/pmic/mc13892/pmic_adc.c
+++ b/drivers/mxc/pmic/mc13892/pmic_adc.c
@@ -248,12 +248,13 @@ static int pmic_adc_suspend(struct platform_device *pdev, pm_message_t state)
 static int pmic_adc_resume(struct platform_device *pdev)
 {
 	/* nothing for mc13892 adc */
-	unsigned int adc_0_reg, adc_1_reg;
+	unsigned int adc_0_reg, adc_1_reg, reg_mask;
 	suspend_flag = 0;
 
 	/* let interrupt of TSI again */
 	adc_0_reg = ADC_WAIT_TSI_0;
-	CHECK_ERROR(pmic_write_reg(REG_ADC0, adc_0_reg, PMIC_ALL_BITS));
+	reg_mask = ADC_WAIT_TSI_0;
+	CHECK_ERROR(pmic_write_reg(REG_ADC0, adc_0_reg, reg_mask));
 	adc_1_reg = ADC_WAIT_TSI_1 | (ADC_BIS * adc_ts);
 	CHECK_ERROR(pmic_write_reg(REG_ADC1, adc_1_reg, PMIC_ALL_BITS));
 
-- 
1.6.0.4