[PATCH 108/133] [Jaunty SRU] ARM.imx51 Freescale:ENGR00113088 MX51:Fix artifacts display issue on CLAA WVGA panel

[Brad Figg]

From: Liu Ying <b17645 at freescale.com>

Change the display data pads to be driven low.

Signed-off-by: Liu Ying <b17645 at freescale.com>
Signed-off-by: Brad Figg <brad.figg at canonical.com>
---
 arch/arm/mach-mx51/mx51_3stack_gpio.c |   98 +++++++++++++++++++++++++++++++++
 1 files changed, 98 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-mx51/mx51_3stack_gpio.c b/arch/arm/mach-mx51/mx51_3stack_gpio.c
index e85979f..c38b5de 100644
--- a/arch/arm/mach-mx51/mx51_3stack_gpio.c
+++ b/arch/arm/mach-mx51/mx51_3stack_gpio.c
@@ -235,6 +235,104 @@ static struct mxc_iomux_pin_cfg __initdata mxc_iomux_pins[] = {
 	{ /* TO2 */
 	MX51_PIN_DI1_PIN13, IOMUX_CONFIG_ALT1,
 	},
+#ifdef CONFIG_FB_MXC_CLAA_WVGA_SYNC_PANEL
+	{
+	 MX51_PIN_DISP1_DAT0, IOMUX_CONFIG_ALT0,
+	 (PAD_CTL_HYS_NONE | PAD_CTL_DRV_LOW | PAD_CTL_SRE_FAST),
+	 },
+	{
+	 MX51_PIN_DISP1_DAT1, IOMUX_CONFIG_ALT0,
+	 (PAD_CTL_HYS_NONE | PAD_CTL_DRV_LOW | PAD_CTL_SRE_FAST),
+	 },
+	{
+	 MX51_PIN_DISP1_DAT2, IOMUX_CONFIG_ALT0,
+	 (PAD_CTL_HYS_NONE | PAD_CTL_DRV_LOW | PAD_CTL_SRE_FAST),
+	 },
+	{
+	 MX51_PIN_DISP1_DAT3, IOMUX_CONFIG_ALT0,
+	 (PAD_CTL_HYS_NONE | PAD_CTL_DRV_LOW | PAD_CTL_SRE_FAST),
+	 },
+	{
+	 MX51_PIN_DISP1_DAT4, IOMUX_CONFIG_ALT0,
+	 (PAD_CTL_HYS_NONE | PAD_CTL_DRV_LOW | PAD_CTL_SRE_FAST),
+	 },
+	{
+	 MX51_PIN_DISP1_DAT5, IOMUX_CONFIG_ALT0,
+	 (PAD_CTL_HYS_NONE | PAD_CTL_DRV_LOW | PAD_CTL_SRE_FAST),
+	 },
+	{
+	 MX51_PIN_DISP1_DAT6, IOMUX_CONFIG_ALT0,
+	 (PAD_CTL_HYS_NONE | PAD_CTL_DRV_LOW | PAD_CTL_SRE_FAST),
+	 },
+	{
+	 MX51_PIN_DISP1_DAT7, IOMUX_CONFIG_ALT0,
+	 (PAD_CTL_HYS_NONE | PAD_CTL_DRV_LOW | PAD_CTL_SRE_FAST),
+	 },
+	{
+	 MX51_PIN_DISP1_DAT8, IOMUX_CONFIG_ALT0,
+	 (PAD_CTL_HYS_NONE | PAD_CTL_DRV_LOW | PAD_CTL_SRE_FAST),
+	 },
+	{
+	 MX51_PIN_DISP1_DAT9, IOMUX_CONFIG_ALT0,
+	 (PAD_CTL_HYS_NONE | PAD_CTL_DRV_LOW | PAD_CTL_SRE_FAST),
+	 },
+	{
+	 MX51_PIN_DISP1_DAT10, IOMUX_CONFIG_ALT0,
+	 (PAD_CTL_HYS_NONE | PAD_CTL_DRV_LOW | PAD_CTL_SRE_FAST),
+	 },
+	{
+	 MX51_PIN_DISP1_DAT11, IOMUX_CONFIG_ALT0,
+	 (PAD_CTL_HYS_NONE | PAD_CTL_DRV_LOW | PAD_CTL_SRE_FAST),
+	 },
+	{
+	 MX51_PIN_DISP1_DAT12, IOMUX_CONFIG_ALT0,
+	 (PAD_CTL_HYS_NONE | PAD_CTL_DRV_LOW | PAD_CTL_SRE_FAST),
+	 },
+	{
+	 MX51_PIN_DISP1_DAT13, IOMUX_CONFIG_ALT0,
+	 (PAD_CTL_HYS_NONE | PAD_CTL_DRV_LOW | PAD_CTL_SRE_FAST),
+	 },
+	{
+	 MX51_PIN_DISP1_DAT14, IOMUX_CONFIG_ALT0,
+	 (PAD_CTL_HYS_NONE | PAD_CTL_DRV_LOW | PAD_CTL_SRE_FAST),
+	 },
+	{
+	 MX51_PIN_DISP1_DAT15, IOMUX_CONFIG_ALT0,
+	 (PAD_CTL_HYS_NONE | PAD_CTL_DRV_LOW | PAD_CTL_SRE_FAST),
+	 },
+	{
+	 MX51_PIN_DISP1_DAT16, IOMUX_CONFIG_ALT0,
+	 (PAD_CTL_HYS_NONE | PAD_CTL_DRV_LOW | PAD_CTL_SRE_FAST),
+	 },
+	{
+	 MX51_PIN_DISP1_DAT17, IOMUX_CONFIG_ALT0,
+	 (PAD_CTL_HYS_NONE | PAD_CTL_DRV_LOW | PAD_CTL_SRE_FAST),
+	 },
+	{
+	 MX51_PIN_DISP1_DAT18, IOMUX_CONFIG_ALT0,
+	 (PAD_CTL_HYS_NONE | PAD_CTL_DRV_LOW | PAD_CTL_SRE_FAST),
+	 },
+	{
+	 MX51_PIN_DISP1_DAT19, IOMUX_CONFIG_ALT0,
+	 (PAD_CTL_HYS_NONE | PAD_CTL_DRV_LOW | PAD_CTL_SRE_FAST),
+	 },
+	{
+	 MX51_PIN_DISP1_DAT20, IOMUX_CONFIG_ALT0,
+	 (PAD_CTL_HYS_NONE | PAD_CTL_DRV_LOW | PAD_CTL_SRE_FAST),
+	 },
+	{
+	 MX51_PIN_DISP1_DAT21, IOMUX_CONFIG_ALT0,
+	 (PAD_CTL_HYS_NONE | PAD_CTL_DRV_LOW | PAD_CTL_SRE_FAST),
+	 },
+	{
+	 MX51_PIN_DISP1_DAT22, IOMUX_CONFIG_ALT0,
+	 (PAD_CTL_HYS_NONE | PAD_CTL_DRV_LOW | PAD_CTL_SRE_FAST),
+	 },
+	{
+	 MX51_PIN_DISP1_DAT23, IOMUX_CONFIG_ALT0,
+	 (PAD_CTL_HYS_NONE | PAD_CTL_DRV_LOW | PAD_CTL_SRE_FAST),
+	 },
+#endif
 	{
 	 MX51_PIN_I2C1_CLK, IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION,
 	 0x1E4,
-- 
1.6.0.4