[PATCH 112/133] [Jaunty SRU] ARM.imx51 Freescale:ENGR00113154 TZIC: Correct Wakeup registers

[Brad Figg]

mxc_cpu_lp_set function writes all enabled interrupts to wakeup
register. But for suspend/resume cases, only allows to write
wakeup resources to wakeup registers.

Signed-off-by: Lily Zhang <r58066 at freescale.com>
Signed-off-by: Brad Figg <brad.figg at canonical.com>
---
 arch/arm/mach-mx51/pm.c |    7 ++++---
 1 files changed, 4 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-mx51/pm.c b/arch/arm/mach-mx51/pm.c
index 3b5787a..bb03d97 100644
--- a/arch/arm/mach-mx51/pm.c
+++ b/arch/arm/mach-mx51/pm.c
@@ -29,9 +29,6 @@ extern int iram_ready;
 
 static int mx51_suspend_enter(suspend_state_t state)
 {
-	if (tzic_enable_wake(0) != 0)
-		return -EAGAIN;
-
 	if (gpc_dvfs_clk == NULL)
 		gpc_dvfs_clk = clk_get(NULL, "gpc_dvfs_clk");
 	/* gpc clock is needed for SRPG */
@@ -46,6 +43,10 @@ static int mx51_suspend_enter(suspend_state_t state)
 	default:
 		return -EINVAL;
 	}
+
+	if (tzic_enable_wake(0) != 0)
+		return -EAGAIN;
+
 	if (state == PM_SUSPEND_MEM) {
 		cpu_do_suspend_workaround();
 		/*clear the EMPGC0/1 bits */
-- 
1.6.0.4