[PATCH 17/133] [Jaunty SRU] ARM.imx51 Freescale:ENGR00109084 IPUv3: Add DP SRM updates when enabling/disabling DP_FG

[Bryan Wu]

Brad Figg wrote:
> From: Liu Ying <b17645 at freescale.com>
> 
> Add DP SRM updates when enabling/disabling DP_FG to fix v4l2 dequeue
> buffer failure issue after playing a video of two frames.
> 
> Signed-off-by: Liu Ying <b17645 at freescale.com>
> Signed-off-by: Brad Figg <brad.figg at canonical.com>
> ---
>  drivers/mxc/ipu3/ipu_disp.c |    5 +++++
>  1 files changed, 5 insertions(+), 0 deletions(-)
> 
> diff --git a/drivers/mxc/ipu3/ipu_disp.c b/drivers/mxc/ipu3/ipu_disp.c
> index f0d1471..19d190b 100644
> --- a/drivers/mxc/ipu3/ipu_disp.c
> +++ b/drivers/mxc/ipu3/ipu_disp.c
> @@ -495,6 +495,8 @@ void _ipu_dp_dc_enable(ipu_channel_t channel)
>  		reg = __raw_readl(DP_COM_CONF(DP_SYNC));
>  		__raw_writel(reg | DP_COM_CONF_FG_EN, DP_COM_CONF(DP_SYNC));
>  
> +		reg = __raw_readl(IPU_SRM_PRI2) | 0x8;

IMHO, 0x8 is meaningless. Can we choose some register bit macro definition for that?

> +		__raw_writel(reg, IPU_SRM_PRI2);
>  		return;
>  	}
>  
> @@ -576,6 +578,9 @@ void _ipu_dp_dc_disable(ipu_channel_t channel)
>  		reg &= ~DP_COM_CONF_FG_EN;
>  		__raw_writel(reg, DP_COM_CONF(DP_SYNC));
>  
> +		reg = __raw_readl(IPU_SRM_PRI2) | 0x8;

Ditto
-Bryan