[3.11.y.z extended stable] Patch "clk: tegra: Fix wrong value written to PLLE_AUX" has been added to staging queue

[Luis Henriques]

This is a note to let you know that I have just added a patch titled

    clk: tegra: Fix wrong value written to PLLE_AUX

to the linux-3.11.y-queue branch of the 3.11.y.z extended stable tree 
which can be found at:

 http://kernel.ubuntu.com/git?p=ubuntu/linux.git;a=shortlog;h=refs/heads/linux-3.11.y-queue

If you, or anyone else, feels it should not be added to this tree, please 
reply to this email.

For more information about the 3.11.y.z tree, see
https://wiki.ubuntu.com/Kernel/Dev/ExtendedStable

Thanks.
-Luis

------

>From e8cd47a944aa956dd58e8e615d58d7abc9e201fd Mon Sep 17 00:00:00 2001
From: Tuomas Tynkkynen <ttynkkynen at nvidia.com>
Date: Fri, 16 May 2014 16:50:20 +0300
Subject: clk: tegra: Fix wrong value written to PLLE_AUX

commit d2c834abe2b39a2d5a6c38ef44de87c97cbb34b4 upstream.

The value written to PLLE_AUX was incorrect due to a wrong variable
being used. Without this fix SATA does not work.

Signed-off-by: Tuomas Tynkkynen <ttynkkynen at nvidia.com>
Tested-by: Mikko Perttunen <mperttunen at nvidia.com>
Reviewed-by: Thierry Reding <treding at nvidia.com>
Tested-by: Thierry Reding <treding at nvidia.com>
Acked-by: Thierry Reding <treding at nvidia.com>
Signed-off-by: Mike Turquette <mturquette at linaro.org>
[mturquette at linaro.org: improved changelog]
[ luis: backported to 3.11: adjusted context ]
Signed-off-by: Luis Henriques <luis.henriques at canonical.com>
---
 drivers/clk/tegra/clk-pll.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c
index 197074a57754..59c39f32bba8 100644
--- a/drivers/clk/tegra/clk-pll.c
+++ b/drivers/clk/tegra/clk-pll.c
@@ -1592,7 +1592,7 @@ struct clk *tegra_clk_register_plle_tegra114(const char *name,
 			  (val & PLLE_AUX_PLLP_SEL) ? "pllp_out0" : "pll_ref");
 	} else {
 		val_aux |= PLLE_AUX_PLLRE_SEL;
-		pll_writel(val, pll_params->aux_reg, pll);
+		pll_writel(val_aux, pll_params->aux_reg, pll);
 	}

 	clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
--
1.9.1