[SRU][Precise][Trusty][Vivid][Wily]xhci: Workaround to get Intel xHCI reset working more reliably

[Andy Whitcroft]

Commit in full:

commit a5964396190d0c40dd549c23848c282fffa5d1f2
Author: Rajmohan Mani <rajmohan.mani at intel.com>
Date:   Wed Nov 18 10:48:20 2015 +0200

    xhci: Workaround to get Intel xHCI reset working more reliably
    
    Existing Intel xHCI controllers require a delay of 1 mS,
    after setting the CMD_RESET bit in command register, before
    accessing any HC registers. This allows the HC to complete
    the reset operation and be ready for HC register access.
    Without this delay, the subsequent HC register access,
    may result in a system hang, very rarely.
    
    Verified CherryView / Braswell platforms go through over
    5000 warm reboot cycles (which was not possible without
    this patch), without any xHCI reset hang.
    
    Signed-off-by: Rajmohan Mani <rajmohan.mani at intel.com>
    Tested-by: Joe Lawrence <joe.lawrence at stratus.com>
    Cc: stable <stable at vger.kernel.org>
    Signed-off-by: Mathias Nyman <mathias.nyman at linux.intel.com>
    Signed-off-by: Greg Kroah-Hartman <gregkh at linuxfoundation.org>

diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c
index 6e7dc6f..dfa44d3 100644
--- a/drivers/usb/host/xhci.c
+++ b/drivers/usb/host/xhci.c
@@ -175,6 +175,16 @@ int xhci_reset(struct xhci_hcd *xhci)
 	command |= CMD_RESET;
 	writel(command, &xhci->op_regs->command);
 
+	/* Existing Intel xHCI controllers require a delay of 1 mS,
+	 * after setting the CMD_RESET bit, and before accessing any
+	 * HC registers. This allows the HC to complete the
+	 * reset operation and be ready for HC register access.
+	 * Without this delay, the subsequent HC register access,
+	 * may result in a system hang very rarely.
+	 */
+	if (xhci->quirks & XHCI_INTEL_HOST)
+		udelay(1000);
+
 	ret = xhci_handshake(&xhci->op_regs->command,
 			CMD_RESET, 0, 10 * 1000 * 1000);
 	if (ret)