[SRU][OEM-6.0][PATCH 1/1] drm/i915: fix TLB invalidation for Gen12 video and compute engines

[Magali Lemes]

From: Andrzej Hajda <andrzej.hajda at intel.com>

In case of Gen12 video and compute engines, TLB_INV registers are masked -
to modify one bit, corresponding bit in upper half of the register must
be enabled, otherwise nothing happens.

CVE: CVE-2022-4139
Suggested-by: Chris Wilson <chris.p.wilson at intel.com>
Signed-off-by: Andrzej Hajda <andrzej.hajda at intel.com>
Acked-by: Daniel Vetter <daniel.vetter at ffwll.ch>
Fixes: 7938d61591d3 ("drm/i915: Flush TLBs before releasing backing store")
Cc: stable at vger.kernel.org
Signed-off-by: Linus Torvalds <torvalds at linux-foundation.org>
CVE-2022-4139
(cherry picked from commit 04aa64375f48a5d430b5550d9271f8428883e550)
Signed-off-by: Magali Lemes <magali.lemes at canonical.com>
---
 drivers/gpu/drm/i915/gt/intel_gt.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
index f435e06125aa..f158f6a08e75 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -961,6 +961,11 @@ static void mmio_invalidate_full(struct intel_gt *gt)
 		if (!i915_mmio_reg_offset(rb.reg))
 			continue;
 
+		if (GRAPHICS_VER(i915) == 12 && (engine->class == VIDEO_DECODE_CLASS ||
+		    engine->class == VIDEO_ENHANCEMENT_CLASS ||
+		    engine->class == COMPUTE_CLASS))
+			rb.bit = _MASKED_BIT_ENABLE(rb.bit);
+
 		intel_uncore_write_fw(uncore, rb.reg, rb.bit);
 		awake |= engine->mask;
 	}
-- 
2.34.1