[SRU][OEM-6.8][Noble][PATCH 1/1] UBUNTU: SAUCE: cpufreq: intel_pstate: Use HWP to initialize ITMT if CPPC is missing

[Aaron Rainbolt]

On 6/24/24 02:02, Aaron Rainbolt wrote:
> From: Rafael J. Wysocki <rafael.j.wysocki at intel.com>
>  
> BugLink: https://bugs.launchpad.net/bugs/2069988
>
> It is reported that single-thread performance on some hybrid systems
> dropped significantly after commit 7feec7430edd ("ACPI: CPPC: Only probe
> for _CPC if CPPC v2 is acked") which prevented _CPC from being used if
> the support for it had not been confirmed by the platform firmware.
>
> The problem is that if the platform firmware does not confirm CPPC v2
> support, cppc_get_perf_caps() returns an error which prevents the
> intel_pstate driver from enabling ITMT.  Consequently, the scheduler
> does not get any hints on CPU performance differences, so in a hybrid
> system some tasks may run on CPUs with lower capacity even though they
> should be running on high-capacity CPUs.
>
> To address this, modify intel_pstate to use the information from
> MSR_HWP_CAPABILITIES to enable ITMT if CPPC is not available (which is
> done already if the highest performance number coming from CPPC is not
> realistic).
>
> Reviewed-by: Mario Limonciello <mario.limonciello at amd.com>
> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki at intel.com>
> Signed-off-by: Aaron Rainbolt <arainbolt at kfocus.org>
>
> ---
>
> diff --git a/drivers/cpufreq/intel_pstate.c b/drivers/cpufreq/intel_pstate.c
> index 79619227e..01046d666 100644
> --- a/drivers/cpufreq/intel_pstate.c
> +++ b/drivers/cpufreq/intel_pstate.c
> @@ -359,15 +359,14 @@ static void intel_pstate_set_itmt_prio(int cpu)
>  	int ret;
>  
>  	ret = cppc_get_perf_caps(cpu, &cppc_perf);
> -	if (ret)
> -		return;
> -
>  	/*
> -	 * On some systems with overclocking enabled, CPPC.highest_perf is hardcoded to 0xff.
> -	 * In this case we can't use CPPC.highest_perf to enable ITMT.
> -	 * In this case we can look at MSR_HWP_CAPABILITIES bits [8:0] to decide.
> +	 * If CPPC is not available, fall back to MSR_HWP_CAPABILITIES bits [8:0].
> +	 *
> +	 * Also, on some systems with overclocking enabled, CPPC.highest_perf is
> +	 * hardcoded to 0xff, so CPPC.highest_perf cannot be used to enable ITMT.
> +	 * Fall back to MSR_HWP_CAPABILITIES then too.
>  	 */
> -	if (cppc_perf.highest_perf == CPPC_MAX_PERF)
> +	if (ret || cppc_perf.highest_perf == CPPC_MAX_PERF)
>  		cppc_perf.highest_perf = HWP_HIGHEST_PERF(READ_ONCE(all_cpu_data[cpu]->hwp_cap_cached));
>  
>  	/*
Holy glitchy mail. Somehow I've managed to make an even bigger mess this time. How the heck do you send a threaded reply correctly in Mutt?!

Sorry for the spam. I'll try to resubmit tomorrow when I can figure out what on earth I'm doing.