[SRU][J:linux-bluefield][PATCH v3 4/9] Revert "UBUNTU: SAUCE: platform/mellanox: mlxbf-tmfifo: Add BlueField-3 support"
Haifei Luo
haifeil at nvidia.com
Mon Mar 24 01:59:21 UTC 2025
BugLink: https://bugs.launchpad.net/bugs/2103386
This reverts commit 3d8185022ec5bdf225c146df13dbcf94c9729f74.
Change-Id: I438083fe2943ec430f260125a1baf2c2bb1380f5
Signed-off-by: Haifei Luo <haifeil at nvidia.com>
---
drivers/platform/mellanox/mlxbf-tmfifo-regs.h | 10 ---
drivers/platform/mellanox/mlxbf-tmfifo.c | 82 +++++--------------
2 files changed, 22 insertions(+), 70 deletions(-)
diff --git a/drivers/platform/mellanox/mlxbf-tmfifo-regs.h b/drivers/platform/mellanox/mlxbf-tmfifo-regs.h
index 1358dad0cfe6..e4f0d2eda714 100644
--- a/drivers/platform/mellanox/mlxbf-tmfifo-regs.h
+++ b/drivers/platform/mellanox/mlxbf-tmfifo-regs.h
@@ -60,14 +60,4 @@
#define MLXBF_TMFIFO_RX_CTL__MAX_ENTRIES_RMASK GENMASK_ULL(8, 0)
#define MLXBF_TMFIFO_RX_CTL__MAX_ENTRIES_MASK GENMASK_ULL(40, 32)
-/* BF3 resource 0 register offset. */
-#define MLXBF_TMFIFO_RX_DATA_BF3 0x0000
-#define MLXBF_TMFIFO_TX_DATA_BF3 0x1000
-
-/* BF3 resource 1 register offset. */
-#define MLXBF_TMFIFO_RX_STS_BF3 0x0000
-#define MLXBF_TMFIFO_RX_CTL_BF3 0x0008
-#define MLXBF_TMFIFO_TX_STS_BF3 0x0100
-#define MLXBF_TMFIFO_TX_CTL_BF3 0x0108
-
#endif /* !defined(__MLXBF_TMFIFO_REGS_H__) */
diff --git a/drivers/platform/mellanox/mlxbf-tmfifo.c b/drivers/platform/mellanox/mlxbf-tmfifo.c
index ffff362fe1c1..767f4406e55f 100644
--- a/drivers/platform/mellanox/mlxbf-tmfifo.c
+++ b/drivers/platform/mellanox/mlxbf-tmfifo.c
@@ -47,9 +47,6 @@
/* Message with data needs at least two words (for header & data). */
#define MLXBF_TMFIFO_DATA_MIN_WORDS 2
-/* ACPI chip identifier for BlueField-3. */
-#define MLXBF_TMFIFO_BF3_UID "1"
-
struct mlxbf_tmfifo;
/**
@@ -153,14 +150,8 @@ struct mlxbf_tmfifo_irq_info {
* mlxbf_tmfifo - Structure of the TmFifo
* @vdev: array of the virtual devices running over the TmFifo
* @lock: lock to protect the TmFifo access
- * @res0: mapped register base for resource 0
- * @res1: mapped register base for resource 1
- * @rx_ctl: TMFIFO_RX_CTL register
- * @rx_sts: TMFIFO_RX_STS register
- * @rx_data: TMFIFO_RX_DATA register
- * @tx_ctl: TMFIFO_TX_CTL register
- * @tx_sts: TMFIFO_TX_STS register
- * @tx_data: TMFIFO_TX_DATA register
+ * @rx_base: mapped register base address for the Rx FIFO
+ * @tx_base: mapped register base address for the Tx FIFO
* @rx_fifo_size: number of entries of the Rx FIFO
* @tx_fifo_size: number of entries of the Tx FIFO
* @pend_events: pending bits for deferred events
@@ -174,14 +165,8 @@ struct mlxbf_tmfifo_irq_info {
struct mlxbf_tmfifo {
struct mlxbf_tmfifo_vdev *vdev[MLXBF_TMFIFO_VDEV_MAX];
struct mutex lock; /* TmFifo lock */
- void __iomem *res0;
- void __iomem *res1;
- void __iomem *rx_ctl;
- void __iomem *rx_sts;
- void __iomem *rx_data;
- void __iomem *tx_ctl;
- void __iomem *tx_sts;
- void __iomem *tx_data;
+ void __iomem *rx_base;
+ void __iomem *tx_base;
int rx_fifo_size;
int tx_fifo_size;
unsigned long pend_events;
@@ -498,7 +483,7 @@ static int mlxbf_tmfifo_get_rx_avail(struct mlxbf_tmfifo *fifo)
{
u64 sts;
- sts = readq(fifo->rx_sts);
+ sts = readq(fifo->rx_base + MLXBF_TMFIFO_RX_STS);
return FIELD_GET(MLXBF_TMFIFO_RX_STS__COUNT_MASK, sts);
}
@@ -515,7 +500,7 @@ static int mlxbf_tmfifo_get_tx_avail(struct mlxbf_tmfifo *fifo, int vdev_id)
else
tx_reserve = 1;
- sts = readq(fifo->tx_sts);
+ sts = readq(fifo->tx_base + MLXBF_TMFIFO_TX_STS);
count = FIELD_GET(MLXBF_TMFIFO_TX_STS__COUNT_MASK, sts);
return fifo->tx_fifo_size - tx_reserve - count;
}
@@ -551,7 +536,7 @@ static void mlxbf_tmfifo_console_tx(struct mlxbf_tmfifo *fifo, int avail)
/* Write header. */
hdr.type = VIRTIO_ID_CONSOLE;
hdr.len = htons(size);
- writeq(*(u64 *)&hdr, fifo->tx_data);
+ writeq(*(u64 *)&hdr, fifo->tx_base + MLXBF_TMFIFO_TX_DATA);
/* Use spin-lock to protect the 'cons->tx_buf'. */
spin_lock_irqsave(&fifo->spin_lock[0], flags);
@@ -568,7 +553,7 @@ static void mlxbf_tmfifo_console_tx(struct mlxbf_tmfifo *fifo, int avail)
memcpy((u8 *)&data + seg, cons->tx_buf.buf,
sizeof(u64) - seg);
}
- writeq(data, fifo->tx_data);
+ writeq(data, fifo->tx_base + MLXBF_TMFIFO_TX_DATA);
if (size >= sizeof(u64)) {
cons->tx_buf.tail = (cons->tx_buf.tail + sizeof(u64)) %
@@ -599,7 +584,7 @@ static void mlxbf_tmfifo_rxtx_word(struct mlxbf_tmfifo_vring *vring,
/* Read a word from FIFO for Rx. */
if (is_rx)
- data = readq(fifo->rx_data);
+ data = readq(fifo->rx_base + MLXBF_TMFIFO_RX_DATA);
if (vring->cur_len + sizeof(u64) <= len) {
/* The whole word. */
@@ -628,7 +613,7 @@ static void mlxbf_tmfifo_rxtx_word(struct mlxbf_tmfifo_vring *vring,
/* Write the word into FIFO for Tx. */
if (!is_rx)
- writeq(data, fifo->tx_data);
+ writeq(data, fifo->tx_base + MLXBF_TMFIFO_TX_DATA);
}
/*
@@ -651,7 +636,7 @@ static void mlxbf_tmfifo_rxtx_header(struct mlxbf_tmfifo_vring *vring,
/* Read/Write packet header. */
if (is_rx) {
/* Drain one word from the FIFO. */
- *(u64 *)&hdr = readq(fifo->rx_data);
+ *(u64 *)&hdr = readq(fifo->rx_base + MLXBF_TMFIFO_RX_DATA);
/* Skip the length 0 packets (keepalive). */
if (hdr.len == 0)
@@ -704,7 +689,7 @@ static void mlxbf_tmfifo_rxtx_header(struct mlxbf_tmfifo_vring *vring,
hdr.type = (vring->vdev_id == VIRTIO_ID_NET) ?
VIRTIO_ID_NET : VIRTIO_ID_CONSOLE;
hdr.len = htons(vring->pkt_len - hdr_len);
- writeq(*(u64 *)&hdr, fifo->tx_data);
+ writeq(*(u64 *)&hdr, fifo->tx_base + MLXBF_TMFIFO_TX_DATA);
}
vring->cur_len = hdr_len;
@@ -1214,7 +1199,7 @@ static void mlxbf_tmfifo_set_threshold(struct mlxbf_tmfifo *fifo)
u64 ctl;
/* Get Tx FIFO size and set the low/high watermark. */
- ctl = readq(fifo->tx_ctl);
+ ctl = readq(fifo->tx_base + MLXBF_TMFIFO_TX_CTL);
fifo->tx_fifo_size =
FIELD_GET(MLXBF_TMFIFO_TX_CTL__MAX_ENTRIES_MASK, ctl);
ctl = (ctl & ~MLXBF_TMFIFO_TX_CTL__LWM_MASK) |
@@ -1223,17 +1208,17 @@ static void mlxbf_tmfifo_set_threshold(struct mlxbf_tmfifo *fifo)
ctl = (ctl & ~MLXBF_TMFIFO_TX_CTL__HWM_MASK) |
FIELD_PREP(MLXBF_TMFIFO_TX_CTL__HWM_MASK,
fifo->tx_fifo_size - 1);
- writeq(ctl, fifo->tx_ctl);
+ writeq(ctl, fifo->tx_base + MLXBF_TMFIFO_TX_CTL);
/* Get Rx FIFO size and set the low/high watermark. */
- ctl = readq(fifo->rx_ctl);
+ ctl = readq(fifo->rx_base + MLXBF_TMFIFO_RX_CTL);
fifo->rx_fifo_size =
FIELD_GET(MLXBF_TMFIFO_RX_CTL__MAX_ENTRIES_MASK, ctl);
ctl = (ctl & ~MLXBF_TMFIFO_RX_CTL__LWM_MASK) |
FIELD_PREP(MLXBF_TMFIFO_RX_CTL__LWM_MASK, 0);
ctl = (ctl & ~MLXBF_TMFIFO_RX_CTL__HWM_MASK) |
FIELD_PREP(MLXBF_TMFIFO_RX_CTL__HWM_MASK, 1);
- writeq(ctl, fifo->rx_ctl);
+ writeq(ctl, fifo->rx_base + MLXBF_TMFIFO_RX_CTL);
}
static void mlxbf_tmfifo_cleanup(struct mlxbf_tmfifo *fifo)
@@ -1253,15 +1238,9 @@ static int mlxbf_tmfifo_probe(struct platform_device *pdev)
{
struct virtio_net_config net_config;
struct device *dev = &pdev->dev;
- struct acpi_device *device;
struct mlxbf_tmfifo *fifo;
- const char *uid;
int i, rc;
- device = ACPI_COMPANION(dev);
- if (!device)
- return -ENODEV;
-
fifo = devm_kzalloc(dev, sizeof(*fifo), GFP_KERNEL);
if (!fifo)
return -ENOMEM;
@@ -1272,31 +1251,14 @@ static int mlxbf_tmfifo_probe(struct platform_device *pdev)
mutex_init(&fifo->lock);
/* Get the resource of the Rx FIFO. */
- fifo->res0 = devm_platform_ioremap_resource(pdev, 0);
- if (IS_ERR(fifo->res0))
- return PTR_ERR(fifo->res0);
+ fifo->rx_base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(fifo->rx_base))
+ return PTR_ERR(fifo->rx_base);
/* Get the resource of the Tx FIFO. */
- fifo->res1 = devm_platform_ioremap_resource(pdev, 1);
- if (IS_ERR(fifo->res1))
- return PTR_ERR(fifo->res1);
-
- uid = acpi_device_uid(device);
- if (uid && !strcmp(uid, MLXBF_TMFIFO_BF3_UID)) {
- fifo->rx_data = fifo->res0 + MLXBF_TMFIFO_RX_DATA_BF3;
- fifo->tx_data = fifo->res0 + MLXBF_TMFIFO_TX_DATA_BF3;
- fifo->rx_sts = fifo->res1 + MLXBF_TMFIFO_RX_STS_BF3;
- fifo->rx_ctl = fifo->res1 + MLXBF_TMFIFO_RX_CTL_BF3;
- fifo->tx_sts = fifo->res1 + MLXBF_TMFIFO_TX_STS_BF3;
- fifo->tx_ctl = fifo->res1 + MLXBF_TMFIFO_TX_CTL_BF3;
- } else {
- fifo->rx_ctl = fifo->res0 + MLXBF_TMFIFO_RX_CTL;
- fifo->rx_sts = fifo->res0 + MLXBF_TMFIFO_RX_STS;
- fifo->rx_data = fifo->res0 + MLXBF_TMFIFO_RX_DATA;
- fifo->tx_ctl = fifo->res1 + MLXBF_TMFIFO_TX_CTL;
- fifo->tx_sts = fifo->res1 + MLXBF_TMFIFO_TX_STS;
- fifo->tx_data = fifo->res1 + MLXBF_TMFIFO_TX_DATA;
- }
+ fifo->tx_base = devm_platform_ioremap_resource(pdev, 1);
+ if (IS_ERR(fifo->tx_base))
+ return PTR_ERR(fifo->tx_base);
platform_set_drvdata(pdev, fifo);
--
2.34.1
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