[PATCH 1/1][SRU][P] platform/x86/amd: pmc: Require at least 2.5 seconds between HW sleep cycles
AceLan Kao
acelan.kao at canonical.com
Thu May 29 00:58:38 UTC 2025
From: Mario Limonciello <mario.limonciello at amd.com>
BugLink: https://bugs.launchpad.net/bugs/2106783
When an APU exits HW sleep with no active wake sources the Linux kernel will
rapidly assert that the APU can enter back into HW sleep. This happens in a
few ms. Contrasting this to Windows, Windows can take 10s of seconds to
enter back into the resiliency phase for Modern Standby.
For some situations this can be problematic because it can cause leakage
from VDDCR_SOC to VDD_MISC and force VDD_MISC outside of the electrical
design guide specifications. On some designs this will trip the over
voltage protection feature (OVP) of the voltage regulator module, but it
could cause APU damage as well.
To prevent this risk, add an explicit sleep call so that future attempts
to enter into HW sleep will have enough time to settle. This will occur
while the screen is dark and only on cases that the APU should enter HW
sleep again, so it shouldn't be noticeable to any user.
Cc: stable at vger.kernel.org
Signed-off-by: Mario Limonciello <mario.limonciello at amd.com>
Acked-by: Shyam Sundar S K <Shyam-sundar.S-k at amd.com>
Link: https://lore.kernel.org/r/20250414162446.3853194-1-superm1@kernel.org
Reviewed-by: Ilpo Järvinen <ilpo.jarvinen at linux.intel.com>
Signed-off-by: Ilpo Järvinen <ilpo.jarvinen at linux.intel.com>
(cherry picked from commit 9f5595d5f03fd4dc640607a71e89a1daa68fd19d)
Signed-off-by: Chia-Lin Kao (AceLan) <acelan.kao at canonical.com>
---
drivers/platform/x86/amd/pmc/pmc.c | 7 +++----
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/drivers/platform/x86/amd/pmc/pmc.c b/drivers/platform/x86/amd/pmc/pmc.c
index e6124498b195f..cfd1c37cf6b6f 100644
--- a/drivers/platform/x86/amd/pmc/pmc.c
+++ b/drivers/platform/x86/amd/pmc/pmc.c
@@ -724,10 +724,9 @@ static void amd_pmc_s2idle_check(void)
struct smu_metrics table;
int rc;
- /* CZN: Ensure that future s0i3 entry attempts at least 10ms passed */
- if (pdev->cpu_id == AMD_CPU_ID_CZN && !get_metrics_table(pdev, &table) &&
- table.s0i3_last_entry_status)
- usleep_range(10000, 20000);
+ /* Avoid triggering OVP */
+ if (!get_metrics_table(pdev, &table) && table.s0i3_last_entry_status)
+ msleep(2500);
/* Dump the IdleMask before we add to the STB */
amd_pmc_idlemask_read(pdev, pdev->dev, NULL);
--
2.43.0
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