[SRU][J][PATCH 03/12] perf vendor events s390: Add cache metrics for z13

[Massimiliano Pellizzer]

From: Thomas Richter <tmricht at linux.ibm.com>

BugLink: https://bugs.launchpad.net/bugs/2103415

Add metrics for s390 z13

- Percentage sourced from Level 2 cache
- Percentage sourced from Level 3 on same chip cache
- Percentage sourced from Level 4 Local cache on same book
- Percentage sourced from Level 4 Remote cache on different book
- Percentage sourced from memory

For details about the formulas see this documentation:

  https://www.ibm.com/support/pages/system/files/inline-files/CPU%20MF%20Formulas%20including%20z16%20-%20May%202022_1.pdf

Output after:

  # ./perf stat -M l4rp -- find /
   ...find output deleted

  Performance counter stats for 'find /':

            2      L1I_OFFDRAWER_SCOL_L4_SOURCED_WRITES #     0.02 l4rp
          252      L1D_ONDRAWER_L4_SOURCED_WRITES
        3,465      L1D_ONDRAWER_L3_SOURCED_WRITES_IV
           80      L1D_OFFDRAWER_SCOL_L4_SOURCED_WRITES
          761      L1D_ONDRAWER_L3_SOURCED_WRITES
            0      L1I_OFFDRAWER_SCOL_L3_SOURCED_WRITES
  131,817,067      L1I_DIR_WRITES
            1      L1I_OFFDRAWER_FCOL_L4_SOURCED_WRITES
          447      L1D_OFFDRAWER_SCOL_L3_SOURCED_WRITES
           22      L1D_OFFDRAWER_FCOL_L4_SOURCED_WRITES
            7      L1I_ONDRAWER_L4_SOURCED_WRITES
            0      L1I_OFFDRAWER_FCOL_L3_SOURCED_WRITES
        1,071      L1D_OFFDRAWER_FCOL_L3_SOURCED_WRITES
            3      L1I_ONDRAWER_L3_SOURCED_WRITES
       13,352      L1D_OFFDRAWER_FCOL_L3_SOURCED_WRITES_IV
       15,252      L1D_OFFDRAWER_SCOL_L3_SOURCED_WRITES_IV
            0      L1I_ONDRAWER_L3_SOURCED_WRITES_IV
            0      L1I_OFFDRAWER_FCOL_L3_SOURCED_WRITES_IV
   57,431,083      L1D_DIR_WRITES
            0      L1I_OFFDRAWER_SCOL_L3_SOURCED_WRITES_IV

      15.386502874 seconds time elapsed

       0.647348000 seconds user
       3.537041000 seconds sys

  #

Signed-off-by: Thomas Richter <tmricht at linux.ibm.com>
Acked-By: Sumanth Korikkar <sumanthk at linux.ibm.com>
Cc: Heiko Carstens <hca at linux.ibm.com>
Cc: Sven Schnelle <svens at linux.ibm.com>
Cc: Vasily Gorbik <gor at linux.ibm.com>
Link: https://lore.kernel.org/r/20230313080201.2440201-3-tmricht@linux.ibm.com
Signed-off-by: Arnaldo Carvalho de Melo <acme at redhat.com>
(cherry picked from commit 850eea236f8ad4a648cb7997eed8a3c616cc0678)
Signed-off-by: Massimiliano Pellizzer <massimiliano.pellizzer at canonical.com>
---
 .../arch/s390/cf_z13/transaction.json         | 25 +++++++++++++++++++
 1 file changed, 25 insertions(+)

diff --git a/tools/perf/pmu-events/arch/s390/cf_z13/transaction.json b/tools/perf/pmu-events/arch/s390/cf_z13/transaction.json
index 86bf83b4504e..71e2c7fa734c 100644
--- a/tools/perf/pmu-events/arch/s390/cf_z13/transaction.json
+++ b/tools/perf/pmu-events/arch/s390/cf_z13/transaction.json
@@ -18,5 +18,30 @@
     "BriefDescription": "Level One Miss per 100 Instructions",
     "MetricName": "l1mp",
     "MetricExpr": "((L1I_DIR_WRITES + L1D_DIR_WRITES) / INSTRUCTIONS) * 100"
+  },
+  {
+    "BriefDescription": "Percentage sourced from Level 2 cache",
+    "MetricName": "l2p",
+    "MetricExpr": "((L1D_L2D_SOURCED_WRITES + L1I_L2I_SOURCED_WRITES) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100"
+  },
+  {
+    "BriefDescription": "Percentage sourced from Level 3 on same chip cache",
+    "MetricName": "l3p",
+    "MetricExpr": "((L1D_ONCHIP_L3_SOURCED_WRITES + L1D_ONCHIP_L3_SOURCED_WRITES_IV + L1I_ONCHIP_L3_SOURCED_WRITES + L1I_ONCHIP_L3_SOURCED_WRITES_IV) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100"
+  },
+  {
+    "BriefDescription": "Percentage sourced from Level 4 Local cache on same book",
+    "MetricName": "l4lp",
+    "MetricExpr": "((L1D_ONNODE_L4_SOURCED_WRITES + L1D_ONNODE_L3_SOURCED_WRITES_IV + L1D_ONNODE_L3_SOURCED_WRITES + L1I_ONNODE_L4_SOURCED_WRITES + L1I_ONNODE_L3_SOURCED_WRITES_IV + L1I_ONNODE_L3_SOURCED_WRITES) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100"
+  },
+  {
+    "BriefDescription": "Percentage sourced from Level 4 Remote cache on different book",
+    "MetricName": "l4rp",
+    "MetricExpr": "((L1D_ONDRAWER_L4_SOURCED_WRITES + L1D_ONDRAWER_L3_SOURCED_WRITES_IV + L1D_ONDRAWER_L3_SOURCED_WRITES + L1D_OFFDRAWER_SCOL_L4_SOURCED_WRITES + L1D_OFFDRAWER_SCOL_L3_SOURCED_WRITES_IV + L1D_OFFDRAWER_SCOL_L3_SOURCED_WRITES + L1D_OFFDRAWER_FCOL_L4_SOURCED_WRITES + L1D_OFFDRAWER_FCOL_L3_SOURCED_WRITES_IV + L1D_OFFDRAWER_FCOL_L3_SOURCED_WRITES + L1I_ONDRAWER_L4_SOURCED_WRITES + L1I_ONDRAWER_L3_SOURCED_WRITES_IV + L1I_ONDRAWER_L3_SOURCED_WRITES + L1I_OFFDRAWER_SCOL_L4_SOURCED_WRITES + L1I_OFFDRAWER_SCOL_L3_SOURCED_WRITES_IV + L1I_OFFDRAWER_SCOL_L3_SOURCED_WRITES + L1I_OFFDRAWER_FCOL_L4_SOURCED_WRITES + L1I_OFFDRAWER_FCOL_L3_SOURCED_WRITES_IV + L1I_OFFDRAWER_FCOL_L3_SOURCED_WRITES) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100"
+  },
+  {
+    "BriefDescription": "Percentage sourced from memory",
+    "MetricName": "memp",
+    "MetricExpr": "((L1D_ONNODE_MEM_SOURCED_WRITES + L1D_ONDRAWER_MEM_SOURCED_WRITES + L1D_OFFDRAWER_MEM_SOURCED_WRITES + L1D_ONCHIP_MEM_SOURCED_WRITES + L1I_ONNODE_MEM_SOURCED_WRITES + L1I_ONDRAWER_MEM_SOURCED_WRITES + L1I_OFFDRAWER_MEM_SOURCED_WRITES + L1I_ONCHIP_MEM_SOURCED_WRITES) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100"
   }
 ]
-- 
2.48.1