Twin dual core XEON reports 8 CPUs on 64bit kernel

[Paul Oppenheim]

>> You do NOT want to disable this in BIOS, you will see a performance 
>> penalty if you do. Linux knows what to do with SMT since kernel ... 
>> 2.6.9 IIRC?
> 
> The performance penalty *might* happen, but there are certain codes
> which are running much much slower with HT enabled. I'm working in
> 
> PS: I guess with standard desktop applications you'll see a performance
> gain!

Technical CPU-architecture explanation follows, not important to 
understanding the issue...

Yes. More specifically, with memory-access intensive operations, your 
CPU cache is effectively divided by the number of thread units you have 
per cache. Thread units swap execution on the CPU in case of a cache 
miss. It is assumed that since the first thread needs to wait to load, 
why not see if the other thread has something useful it can do in the 
cache? The problem comes when both threads are thrashing the cache. If 
you had a single-thread, it would just wait for the memory load. With 2 
threads and one cache, they have to share that same cache. Multi-core 
chips are based on the same idea, except they execute in parallel, but 
still share the same cache. This is why many multi-core chips have 
multi-megabyte caches. They still might end up stalled on a cache miss!

In the end you get more work done (in aggregate, not in a single thread) 
than you get with faster single-core / single-thread CPUs and their huge 
branch prediction logic and deep pipelining. However, single-thread 
execution suffers, and if your threads just need lots of cache (as in 
the case of many sci apps) then you should probably give each thread as 
much cache as you can. Get a Power5 (32 MB chip cache :P)

Yeah, that may have been too deep of a discussion for the question...

+ paul