[PATCH] dmicheck: minor code style clean-ups, no functional changes

[Ivan Hu]

Signed-off-by: Ivan Hu <ivan.hu at canonical.com>
---
 src/dmi/dmicheck/dmicheck.c | 25 +++++++++++++------------
 1 file changed, 13 insertions(+), 12 deletions(-)

diff --git a/src/dmi/dmicheck/dmicheck.c b/src/dmi/dmicheck/dmicheck.c
index 03f8ef14..f6a37e30 100644
--- a/src/dmi/dmicheck/dmicheck.c
+++ b/src/dmi/dmicheck/dmicheck.c
@@ -1438,9 +1438,9 @@ static void dmicheck_entry(fwts_framework *fw,
 			dmi_str_check(fw, table, addr, "Socket Designation", hdr, 0x4);
 			dmi_min_max_uint8_check(fw, table, addr, "Processor Type", hdr, 0x5, 0x1, 0x6);
 			dmi_min_max_uint8_check(fw, table, addr, "Processor Family", hdr, 0x6, 0x1, 0xfe);
-			dmi_str_check(fw, table, addr, "Processor Manufacturer", hdr, 0x7);
+			dmi_str_check(fw, table, addr, "Processor Manufacturer", hdr, 0x7);	
+#ifdef FWTS_ARCH_AARCH64
 			/* Check for Processor ID */
-			#ifdef FWTS_ARCH_AARCH64
 			if (hdr->length >= 0x28)
 			{
 				/* Get "Processor Characteristics" and check 9th bit if Arm64 SoC ID is supported */
@@ -1456,21 +1456,22 @@ static void dmicheck_entry(fwts_framework *fw,
 							"According to the configured \"Processor Characteristics\", Arm64 SoC ID is supported "
 							"however, the SoC revision value is 0x%8.8" PRIx32 " . Non-zero expected.",
 							processor_ID_second_DWORD );
-						
+
 						fwts_advice(fw,
 							"Arm64 SoC ID support is configured to true in \"Processor Characteristics\" "
 							"however, the SiP SoC revision value is 0. "
 							"It is possible that the system is not correctly configured for "
 							"Arm64 SoC ID and still has the old configuration of "
-							"MIDR_EL1 register. If Arm64 SoC ID is indeed not supported " 
+							"MIDR_EL1 register. If Arm64 SoC ID is indeed not supported "
 							"then reset the bit in \"Processor Characteristics\".");
-					}	
+					}
 				}
 				else
 				{
-					/* Arm64 SoC ID is NOT Supported
-					 *  First DWORD should have contents of MIDR_EL1
-					 *  Second DWORD is reserved and must be 0
+					/* 
+					 * Arm64 SoC ID is NOT Supported
+					 * First DWORD should have contents of MIDR_EL1
+					 * Second DWORD is reserved and must be 0
 					 */
 					if (processor_ID_second_DWORD != 0 )
 					{
@@ -1478,10 +1479,10 @@ static void dmicheck_entry(fwts_framework *fw,
 							"According to the configured \"Processor Characteristics\" Arm64 SoC ID is NOT supported "
 							"however, the DWORD in offset is 0Ch-0Fh is non-zero: 0x%8.8" PRIx32 " ",
 							processor_ID_second_DWORD );
-					
+
 						fwts_advice(fw,
 							"Arm64 SoC ID support is configured to false in \"Processor Characteristics\" "
-							"however, the DWORD in offset is 0Ch-0Fh is non-zero. Configure the " 
+							"however, the DWORD in offset is 0Ch-0Fh is non-zero. Configure the "
 							"\"Processor Characteristics\" "
 							"correctly if Arm64 SoC ID is indeed supported in the system.");
 					}
@@ -1491,14 +1492,14 @@ static void dmicheck_entry(fwts_framework *fw,
 							"According to the configured \"Processor Characteristics\" Arm64 SoC ID is NOT supported "
 							"however, the DWORD in offset is 08h-0bh is zero: 0x%8.8" PRIx16 " This should contain MIDR_EL1 value",
 							processor_ID_first_DWORD );
-					
+
 						fwts_advice(fw,
 							"Arm64 SoC ID support is configured to false in \"Processor Characteristics\" "
 							"however, the DWORD in offset is 08h-0bh is zero. This must contain MIDR_EL1");
 					}
 				}
 			}
-			#endif
+#endif
 			dmi_str_check(fw, table, addr, "Processor Version", hdr, 0x10);
 			if (((GET_UINT8(data + 0x18) & 0x07) == 0x5) || ((GET_UINT8(data + 0x18) & 0x07) == 0x6))
 				fwts_failed(fw, LOG_LEVEL_HIGH, DMI_VALUE_OUT_OF_RANGE,
-- 
2.34.1